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2 Meg x 8 Smart 5 Even-Sectored Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F42.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
YES
NO
VPP = 5V
V
PP VCC
Complete Status
Check (optional)
ERASE Complete
NO
YES
Suspend ERASE?
STATUS REGISTER
or RY/BY# Polling
SR7 = 1?
WRITE 20H
Start
WRITE D0H,
Block Address
Suspend
Sequence
ERASE Resumed
ERASE
Busy
3
4
2
SELF-TIMED BLOCK ERASE SEQUENCE
1
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
NO
Start (BLOCK ERASE completed)
YES
SR4, 5 = 1?
SR3 = 0?
YES
YES
Command Sequence Error
SR5 = 0?
NO
6
6
V Error
PP
BLOCK ERASE
5, 6
ERASE Successful
NOTE: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required.
3. To return to the array read mode, the FFH command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER (50H) should be issued before further
WRITE or ERASE operations are attempted.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
