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2 Meg x 8 Smart 5 Even-Sectored Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F42.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
INPUT OPERATIONS
The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control the
mode of operation of the device. A WRITE is used to
input data to the memory array. The following section
describes both types of inputs. More information de-
scribing how to use the two types of inputs to write or
erase the device is provided in the Command Execution
section.
COMMANDS
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM. The 8-bit command is input on DQ0-DQ7
and is latched on the rising edge of CE# (CE#-con-
trolled) or WE# (WE#-controlled), whichever occurs
first.
MEMORY ARRAY
A WRITE to the memory array sets the desired bits to
logic 0s but cannot change a given bit to a logic 1 from
a logic 0. Setting any bits to a logic 1 requires that the
entire block be erased. To perform a WRITE, OE# must
be HIGH, CE# and WE# must be LOW, and VPP must be
set to VPPH (5V). A0-A20 provide the address to be
written, while the data to be written to the array is input
on the DQ pins. The data and addresses are latched on
the rising edge of either CE# (CE#-controlled) or WE#
(WE#-controlled), whichever occurs first. A WRITE must
be preceded by a WRITE SETUP command. Details on
how to input data to the array will be covered in the
Write Sequence section.
COMMAND SET
To simplify writing of the memory blocks, the
MT28F016S5 incorporates an ISM that controls all
internal algorithms for the WRITE and ERASE cycles.
An 8-bit command set is used to control the device.
Details on how to sequence commands are provided in
the Command Execution section. Table 1 lists the valid
commands.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled to
check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation will output the status
register contents on DQ0-DQ7 without prior com-
mand. While the status register contents are read, the
outputs will not be updated if there is a change in the
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend, status register or
read mode, READ STATUS REGISTER (70H) can be
issued to view the status register contents.
All of the defined bits are set by the ISM, but only the
ISM and erase suspend status bits are reset by the ISM.
The erase, write and VPP status bits must be cleared
using CLEAR STATUS REGISTER (50H). This allows the
user to choose when to poll and clear the status register.
For example, the host system may perform multiple
WRITE operations before checking the status register
instead of checking after each individual WRITE. As-
serting the RP# signal or powering down the device will
also clear the status register.
DEVICE CONFIGURATION REGISTERS
The device ID and manufacturer compatibility ID
can be read by issuing READ DEVICE CONFIGURA-
TION (90H). To read the desired register, a specific
address must be asserted. See Table 3 for more details on
the various device configuration registers.
