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2 Meg x 8 Smart 5 Even-Sectored Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F42.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
ERASE SEQUENCE
Executing an ERASE sequence will set all bits within
a block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To
provide added security against accidental block era-
sure, two consecutive command cycles are required to
initiate an ERASE of a block. In the first cycle, addresses
are “Don’t Care,” and ERASE SETUP (20H) is given. In
the second cycle, VPP is brought to VPPH, an address
within the block to be erased is issued, and ERASE
CONFIRM (D0H) is given. If a command other than
ERASE CONFIRM is given, the write and erase status bits
(SR4 and SR5) will be set, and the device will be in the
read status mode.
After the ERASE CONFIRM (D0H) is issued, the ISM
will start the ERASE of the addressed block. Any READ
operation will output the status register contents on
DQ0-DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1 and RY/BY# = VOH). Once the ERASE
is completed, the device will be in the status register
read mode until another command is issued.
ERASE SUSPENSION
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command
allows other commands to be executed while pausing
the ERASE in progress. Once the device has reached the
suspend mode, the erase suspend status bit (SR6) and
ISM status bit (SR7) will be set and RY/BY# will transi-
tion to VOH. The device may now be given a READ
ARRAY, ERASE RESUME or READ STATUS REGISTER
command. After READ ARRAY has been issued, any
location not within the block being erased may be read.
If ERASE RESUME is issued before SR6 has been set, the
device will immediately proceed with the ERASE in
progress. During an ERASE SUSPEND, VPP and RP# must
remain at the same levels used for the ERASE.
ERROR HANDLING
After the ISM status bit (SR7) has been set, VPP (SR3),
write (SR4) and erase (SR5) status bits may be checked.
If one or a combination of these four bits has been set,
an error has occurred. The ISM cannot reset these four
bits. To clear these bits, CLEAR STATUS REGISTER
(50H) must be given. Table 6 lists the combination of
errors.
WRITE/ERASE CYCLE ENDURANCE
The MT28F016S5 is designed and fabricated to meet
advanced firmware and data storage requirements. To
ensure this level of reliability, VPP must be at 5V ±10%
during WRITE or ERASE cycles. For SmartVoltage-
compatible production programming, 12V VPP is sup-
ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. Operation
outside these limits may reduce the number of WRITE
and ERASE cycles that can be performed on the device.
POWER USAGE
The MT28F016S5 offers several power-saving fea-
tures that may be utilized in the array read mode to
conserve power. Deep power-down mode is enabled by
bringing RP# to VSS ±0.2V. Current draw (ICC) in this
mode is a maximum of 10µA. When CE# is HIGH, the
device will enter standby mode. In this mode, maxi-
mum ICC current is 100µA. If CE# is brought HIGH
during a WRITE or ERASE, the ISM will continue to
operate, and the device will consume the respective
active power until the WRITE or ERASE is completed.
POWER-UP
The likelihood of unwanted WRITE or ERASE opera-
tions is minimized since two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC
is ramping, one of the following conditions must be
met:
• RP# must be held LOW until VCC is at valid func-
tional level; or
• CE# or WE# may be held HIGH and
RP# must be toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is reset,
and the device will enter the array read mode.
Figure 2
Power-Up/Reset Timing Diagram
VALID
VALID
V
CC
(5V)
Data
Address
UNDEFINED
t
Note 1
RP#
RWH
t
AA
NOTE: 1. V
CC
must be within the valid operating range before RP#
oes HIGH.
