5
2 Meg x 8 Smart 5 Even-Sectored Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F42.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F016S5 flash memory incorporates a num-
ber of features that make it ideally suited for system
firmware or data storage. The memory array is seg-
mented into individual erase blocks. Each block may be
erased without affecting data stored in other blocks.
These memory blocks are read, written and erased by
issuing commands to the command execution logic
(CEL). The CEL controls the operation of the internal
state machine (ISM), which completely controls all
WRITE, BLOCK ERASE and VERIFY operations. The ISM
protects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
an external programmer.
The Functional Description provides detailed infor-
mation on the operation of the MT28F016S5 and is
organized into these sections:
• Overview
• Memory Architecture
• Output (READ) Operations
• Input Operations
• Command Set
• ISM Status Register
• Device Configuration Registers
• Command Execution
• Error Handling
• WRITE/ERASE Cycle Endurance
• Power Usage
• Power-Up
OVERVIEW
SMART 5 TECHNOLOGY
Smart 5 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. For 5V-
only systems, WRITE and ERASE operations may be
executed with a VPP voltage of 5V. Due to process
technology advances, 5V VPP is optimal for application
and production programming. For backward compat-
ibility with SmartVoltage technology, 12V VPP is sup-
ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. However,
no performance increase is realized. For any operation,
VCC is at 5V.
THIRTY-TWO INDEPENDENTLY ERASABLE
MEMORY BLOCKS
The MT28F016S5 is organized into 32 indepen-
dently erasable memory blocks that allow portions of
the memory to be erased without affecting the rest of
the memory data.
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and WRITE timing are simplified
with an ISM that controls all erase and write algorithms
in the memory array. The ISM ensures protection against
over-erasure and optimizes write margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When a BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor
to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These two bits
indicate whether the ISM is busy with an ERASE or
WRITE task and when an ERASE has been suspended.
Additional error information is set in three other bits:
VPP status, erase status and write status. These three bits
must be cleared by the host system.
READY/BUSY# (RY/BY#) OUTPUT
In addition to status register polling, the MT28F016S5
provides an asynchronous RY/BY# output to indicate
the status of the ISM. RY/BY# is VOH when the state
machine is inactive and VOL during a WRITE or ERASE
operation. This output is always active.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, device
configuration or status register). Commands may be
issued to the CEL while the ISM is active. However,
there are restrictions on what commands are allowed in
this condition. See the Command Execution section for
more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F016S5 features a very low current, deep power-
down mode. To enter this mode, the RP# pin is taken to
VSS ±0.2V. In this mode, the current draw is a maximum
of 10µA. Entering deep power-down also clears the
status register and sets the ISM to the read array mode.
