Pin Function
D0–D5 Preset Data Inputs
Q0–Q5 Differential Data Outputs
S1, S2 Mode Control Pins
MR Master Reset
CLK Clock Input
COUT, COUT Carry Out Output (Active LOW)
CLOUT Look-Ahead-Carry Output
CIN Carry-In Input (Active LOW)
CLIN Look-Ahead-Carry Input
V
CCO VCC to Output
DESCRIPTION
FEATURES
■ 550MHz count frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ Look-ahead-carry input and output
■ Fully synchronous up and down counting
■ Asynchronous Master Reset
■ Internal 75KΩ input pull-down resistors
■ Available in 28-pin PLCC package
The SY10/100E136 are 6-bit synchronous, presettable,
cascadable universal counters. These devices generate
a look-ahead-carry output and accept a look-ahead-carry
input. These two features allow for the cascading of
multiple E136s for wider bit width counters that operate
at very nearly the same frequency as the stand-alone
counter.
The CLOUT output will pulse LOW for one clock cycle
one count before the E136 reaches terminal count. The
COUT output will pulse LOW for one clock cycle when
the counter reaches terminal count. For more information
on utilizing the look-ahead-carry features of the device,
please refer to the applications section of this data sheet.
The differential COUT output facilitates the E136's use in
programmable divider and self-stopping counter
applications.
Unlike the H136 and other similar universal counter
designs, the E136 carry-out and look-ahead-carry-out
signals are registered on chip. This design alleviates the
glitch problem seen on many counters where the carry-
out signals are merely gated. Because of this architecture,
there are some minor functional differences between the
E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet
carefully. Note specifically (see block diagram) the
operation of the carry-out outputs and the look-ahead-
carry-in input when utilizing the Master Reset.
When left open, all of the input pins will be pulled
LOW via an input pulldown resistor. The Master Reset is
an asynchronous signal which, when asserted, will force
the Q outputs LOW.
The Q outputs need not be terminated for the E136 to
function properly. In fact, if these outputs will not be
used in a system, it is recommended that they be left
open to save power and minimize noise. This practice
will minimize switching noise which can reduce the
maximum count frequency of the device, or significantly
reduce margins against other noise in the system.
PIN CONFIGURATION
PIN NAMES
SY10E136
SY100E136
6-BIT UNIVERSAL
UP/DOWN COUNTER
Rev.: C Amendment: /1
Issue Date: February, 1998
D4
VEE
D2
S2
CIN
CL
Q4
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
567891011
CLIN
S1
VCCO
Q1
Q3
Q5
PLCC
TOP VIEW
J28-1
D3
VCCO
D5
Q2
VCC
VCCO
COUT
COUT
CLOUT
Q0
VCCO
D0
D1
MR
V
CCO
1
