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SY10E143JC

Part # SY10E143JC
Description IC HOLD REGISTER 9-BIT 28-PLCC
Category IC
Availability In Stock
Qty 438
Qty Price
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Manufacturer Available Qty
SYNERGY
Date Code: 26
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

700MHz min. operating frequency
Extended 100E VEE range of –4.2V to –5.5V
9 bits wide for byte-parity applications
Asynchronous Master Reset
Dual clocks
Fully compatible with industry standard 10KH,
100K ECL levels
Internal 75k input pulldown resistors
Fully compatible with Motorola MC10E/100E143
Available in 28-pin PLCC package
FEATURES
9-BIT HOLD
REGISTER
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D0-D8, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK1 or CLK2.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring high-
speed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
DESCRIPTION
SY10E143
SY100E143
Rev.: D Amendment: /0
Issue Date: August, 1998
PIN CONFIGURATION
PIN NAMES
Pin Function
D0-D8 Parallel Data Inputs
SEL Mode Select Input
CLK1, CLK2 Clock Inputs
MR Master Reset
Q0-Q8 Data Outputs
NC No Connection
V
CCO VCC to Output
BLOCK DIAGRAM
VEE
MR
CLK
1
D0
NC
VCCO
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
567891011
D1
CLK2
Q2
Q1
Q7
D5
PLCC
TOP VIEW
J28-1
SEL
D
6
D7
Q6
VCC
Q5
VCCO
Q4
Q3
Q0
VCCO
D4
D3
D2
D8
Q8
D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SEL
MR
D
0
D1
D2
D3
D4
D5
D6
D7
D8
CLK1
CLK2
D
D
R
D
R
D
R
D
R
D
R
D
R
D
R
R
R
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
1
2
SY10E143
SY100E143
Micrel
TRUTH TABLE
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
SEL MODE
L LOAD
H HOLD
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current 150 150 150 µA—
I
EE Power Supply Current mA
10E 120 145 120 145 120 145
100E 120 145 120 145 138 165
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
fMAX Max. Toggle Frequency 700 900 700 900 700 900 MHz
t
PLH Propagation Delay to Output ps
tPHL CLK 600 800 1000 600 800 1000 600 800 1000
MR 600 800 1000 600 800 1000 600 800 1000
t
S Set-up Time ps
D 50 –100 50 –100 50 –100
SEL 300 150 300 150 300 150
t
H Hold Time ps
D 300 100 300 100 300 100
SEL 75 –150 75 –150 75 –150
tRR Reset Recovery Time 900 700 900 700 900 700 ps
t
PW Minimum Pulse Width 400 400 400 ps
CLK, MR
tskew Within-Device Skew 75 75 75 ps 1
t
r Rise/Fall Time 300 525 800 300 525 800 300 525 800 ps
tf 20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E143JC J28-1 Commercial
SY10E143JCTR J28-1 Commercial
SY100E143JC J28-1 Commercial
SY100E143JCTR J28-1 Commercial
3
SY10E143
SY100E143
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
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