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AT45DB321D-MU

Part # AT45DB321D-MU
Description FLASH, 32MB, DFN-8, Memory Size:32Mbit, Flash Memory Confi
Category IC
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Technical Document


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4
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
FLASH MEMORY ARRAY
PAGE (512/528 BYTES)
BUFFER 2 (512/528 BYTES)BUFFER 1 (512/528 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SOSI
SECTOR 0a = 8 Pages
4,096/4,224 bytes
SECTOR 0b = 120 Pages
61,440/63,360 bytes
Block = 4,096/4,224 bytes
8 Pages
SECTOR 0a
SECTOR 0b
Page = 512/528 bytes
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 8,190
PAGE 8,191
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 1 8
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1,022
BLOCK 1,023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
SECTOR 1
SECTOR 63 = 128 Pages
65,536/67,586 bytes
BLOCK 2
SECTOR 1 = 128 Pages
65,536/67,584 bytes
SECTOR 62 = 128 Pages
65,536/67,584 bytes
SECTOR 2 = 128 Pages
65,536/67,584 bytes
5
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-7 on
page 31. A valid instruction starts with the falling edge of CS
followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS
pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main memory
address location through the SI (serial input) pin. All instructions, addresses, and data are trans-
ferred with the most significant bit (MSB) first.
Buffer addressing for the DataFlash standard page size (528 bytes) is referenced in the
datasheet using the terminology BFA9 - BFA0 to denote the 10 address bits required to desig-
nate a byte address within a buffer. Main memory addressing is referenced using the
terminology PA12 - PA0 and BA9 - BA0, where PA12 - PA0 denotes the 13 address bits
required to designate a page address and BA9 - BA0 denotes the 10 address bits required to
designate a byte address within the page.
For “Power of 2” binary page size (512 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA8 - BFA0 to denote the 9 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A21 - A0, where A21 - A9 denotes the 13 address bits required to desig-
nate a page address and A8 - A0 denotes the 9 address bits required to designate a byte
address within a page.
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and
Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for
details on the clock cycle sequences for each mode.
6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (528 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The
first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main mem-
ory array to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the
starting byte address within the page. To perform a continuous read from the binary page size
(512 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes
and 4 don’t care bytes. The first 13 bits (A21 - A9) of the 22-bits sequence specify which page of
the main memory array to read, and the last 9 bits (A8 - A0) of the 22-bits address sequence
specify the starting byte address within the page. The don’t care bytes that follow the address
bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS
pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
6
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with cross-
ing over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS
pin will terminate the read operation and tri-state the output
pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by
the f
CAR1
specification. The Continuous Array Read bypasses both data buffers and leaves the
contents of the buffers unchanged.
6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by f
CAR1
. To perform a
continuous read array with the page size set to 528 bytes, the CS
must first be asserted then an
opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the
main memory array to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence
specify the starting byte address within the page. To perform a continuous read with the page
size set to 512 bytes, the opcode, 0BH, must be clocked into the device followed by three
address bytes (A21 - A0) and a dummy byte. Following the dummy byte, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the f
CAR1
specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by f
CAR2
. To perform a continuous
read array with the page size set to 528 bytes, the CS
must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 13 bits (PA12 - PA0) of the 23-bit address sequence
specify which page of the main memory array to read, and the last 10 bits (BA9 - BA0) of the
23-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 512 bytes, the opcode, 03H, must be clocked into the device
followed by three address bytes (A21 - A0). Following the address bytes, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
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