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AT45DB321D-MU

Part # AT45DB321D-MU
Description FLASH, 32MB, DFN-8, Memory Size:32Mbit, Flash Memory Confi
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

19
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
10.1.1 Sector Lockdown Register
Sector Lockdown Register is a nonvolatile register that contains 64 bytes of data, as shown
below:
10.1.2 Reading the Sector Lockdown Register
The Sector Lockdown Register can be read to determine which sectors in the memory array are
permanently locked down. To read the Sector Lockdown Register, the CS
pin must first be
asserted. Once the CS
pin has been asserted, an opcode of 35H and 3 dummy bytes must be
clocked into the device via the SI pin. After the last bit of the opcode and dummy bytes have
been clocked in, the data for the contents of the Sector Lockdown Register will be clocked out
on the SO pin. The first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to
sector 1 and the last byte (byte 16) corresponds to sector 15. After the last byte of the Sector
Lockdown Register has been read, additional pulses on the SCK pin will simply result in unde-
fined data being output on the SO pin.
Deasserting the CS
pin will terminate the Read Sector Lockdown Register operation and put the
SO pin into a high-impedance state.
Table 10-2 details the values read from the Sector Lockdown Register.
Figure 10-2. Read Sector Lockdown Register
Sector Number 0 (0a, 0b) 1 to 63
Locked
See Below
FFH
Unlocked 00H
Table 10-1. Sector 0 (0a, 0b)
0a 0b
Bit 3, 2
Data
Value
(Pages 0-7) (Pages 8-127)
Bit 7, 6 Bit 5, 4 Bit 1, 0
Sectors 0a, 0b Unlocked 00 00 00 00 00H
Sector 0a Locked (Pages 0-7) 11 00 00 00 C0H
Sector 0b Locked (Pages 8-127) 00 11 00 00 30H
Sectors 0a, 0b Locked (Pages 0-127) 11 11 00 00 F0H
Table 10-2. Sector Lockdown Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Read Sector Lockdown Register 35H xxH xxH xxH
Note: xx = Dummy Byte
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + 63
SI
SO
Each transition
represents 8 bits
20
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
10.2 Security Register
The device contains a specialized Security Register that can be used for purposes such
as unique device serialization or locked key storage. The register is comprised of a total of
128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the
Security Register are allocated as a one-time user programmable space. Once these 64 bytes
have been programmed, they cannot be reprogrammed. The remaining 64 bytes of the register
(byte locations 64 through 127) are factory programmed by Atmel and will contain a unique
value for each device. The factory programmed data is fixed and cannot be changed.
10.2.1 Programming the Security Register
The user programmable portion of the Security Register does not need to be erased before it is
programmed.
To program the Security Register, the CS
pin must first be asserted and the appropriate 4-byte
opcode sequence must be clocked into the device in the correct order. The 4-byte opcode
sequence must start with 9BH and be followed by 00H, 00H, and 00H. After the last bit of the
opcode sequence has been clocked into the device, the data for the contents of the 64-byte user
programmable portion of the Security Register must be clocked in.
After the last data byte has been clocked in, the CS
pin must be deasserted to initiate the inter-
nally self-timed program cycle. The programming of the Security Register should take place in a
time of t
P
, during which time the Status Register will indicate that the device is busy. If the device
is powered-down during the program cycle, then the contents of the 64-byte user programmable
portion of the Security Register cannot be guaranteed.
If the full 64 bytes of data is not clocked in before the CS
pin is deasserted, then the values of
the byte locations not clocked in cannot be guaranteed. For example, if only the first two bytes
are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user pro-
grammable portion of the Security Register cannot be guaranteed. Furthermore, if more than
64 bytes of data is clocked into the device, then the data will wrap back around to the beginning
of the register. For instance, if 65 bytes of data are clocked in, then the 65th byte will be stored at
byte location 0 of the Security Register.
The user programmable portion of the Security Register can only be programmed one
time. Therefore, it is not possible to only program the first two bytes of the register and then pro-
gram the remaining 62 bytes at a later time.
The Program Security Register command utilizes the internal SRAM buffer 1 for processing.
Therefore, the contents of the buffer 1 will be altered from its previous state when this command
is issued.
Figure 10-3. Program Security Register
Table 10-3. Security Register
Security Register Byte Number
01• • • 62 63 64 65 • • • 126 127
Data Type One-time User Programmable Factory Programmed By Atmel
Data Byte
n
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n + 1
Data Byte
n + x
CS
Each transition
represents 8 bits
SI
21
3597H–DFLASH–02/07
AT45DB321D [Preliminary]
10.2.2 Reading the Security Register
The Security Register can be read by first asserting the CS
pin and then clocking in an opcode
of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the con-
tent of the Security Register can be clocked out on the SO pins. After the last byte of the
Security Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pins.
Deasserting the CS
pin will terminate the Read Security Register operation and put the SO pins
into a high-impedance state.
Figure 10-4. Read Security Register
11. Additional Commands
11.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation for the DataFlash standard page size (528 bytes), a 1-byte opcode, 53H for buffer
1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-
prised of 1 don’t care bit, 13-page address bit (PA12 - PA0), which specify the page in main
memory that is to be transferred, and 10 don’t care bits. To perform a main memory page to
buffer transfer for the binary page size (512 bytes), the opcode 53H for buffer 1 or 55H for buffer
2, must be clocked into the device followed by three address bytes consisting of 2 don’t care
bits, 13-page address bits (A21 - A9) which specify the page in the main memory that is to be
transferred, and 9 don’t care bits. The CS
pin must be low while toggling the SCK pin to load the
opcode and the address bytes from the input pin (SI). The transfer of the page of data from the
main memory to the buffer will begin when the CS
pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (t
XFR
), the status register can be read or the RDY/BUSY can be
monitored to determine whether the transfer has been completed.
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + x
Each transition
represents 8 bits
SI
SO
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