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ADF4112BRU

Part # ADF4112BRU
Description PLL FREQ SYNTHESIZER SGL 16TSSOP - Rail/Tube
Category IC
Availability In Stock
Qty 9
Qty Price
1 + $2.04903
Manufacturer Available Qty
Analog Devices
Date Code: 0234
  • Shipping Freelance Stock: 7
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Analog Devices
Date Code: 0414
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
13
Table III. Reference Counter Latch Map
OPERATION
LDP
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
0
1
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
R14
0
0
0
0
1
1
1
1
R13
0
0
0
0
1
1
1
1
R12
0
0
0
0
1
1
1
1
R3
0
0
0
1
1
1
1
1
R2
0
1
1
0
0
0
1
1
R1
1
0
1
0
0
1
0
1
DIVIDE RATIO
1
2
3
4
16380
16381
16382
16383
••••••••••
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••••••••••
TEST
MODE BITS
DB23 DB22
DB21
DB20 DB19 DB18
DB17
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
DB6
DB5
DB4 DB3
DB13
LDP T2 T1 R14 R13 R12 R11 R10 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)R9
14-BIT REFERENCE COUNTER
CONTROL
BITS
RESERVED
DB2 DB1
DB0
SYNCDLY ABP2 ABP1
ANTI-
BACKLASH
WIDTH
SYNC
DLY
LOCK
DETECT
PRECISION
ABP1ABP2
0
0
1
1
0
1
0
1
3.0ns
1.5ns
6.0ns
3.0ns
ANTIBACKLASH PULSEWIDTH
SYNCDLY
0
0
1
1
0
1
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
OPERATION
X
X = DON'T
CARE
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
14
Table IV. AB Counter Latch Map
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
A6
0
0
0
0
1
1
1
1
A5
0
0
0
0
1
1
1
1
A2
0
0
1
1
0
0
1
1
A1
0
1
0
1
0
1
0
1
A COUNTER
DIVIDE RATIO
0
1
2
3
60
61
62
63
••••••••••
••••••••••
••••••••••
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••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
B13
0
0
0
0
0
1
1
1
1
B12
0
0
0
0
0
1
1
1
1
B11
0
0
0
0
0
1
1
1
1
B3 B2 B1 B COUNTER DIVIDE RATIO••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
4
8188
8189
8190
8191
13-BIT B COUNTER
DB23 DB22
DB21
DB20 DB19 DB18
DB17
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
DB6
DB5 DB4 DB3DB13
B13 B12 B11 B8 B7 B6 B5 B4 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)B3
6-BIT A COUNTER
CONTROL
BITS
RESERVED
DB2 DB1
DB0
G1 B10 B9
CP GAIN
*SEE TABLE 5
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
CP GAIN OPERATION
0
0
1
1
0
1
0
1
CHARGE PUMP CURRENT
SETTTING 1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (N
X
F
REF
), AT THE OUTPUT, N
MIN
IS (P
2
-P).
X
X = DON'T CARE
X
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
15
Table V. Function Latch Map
M3
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SERIAL DATA OUTPUT
DGND
F1
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
F2
0
1
PD POLARITY
NEGATIVE
POSITIVE
F3
0
1
CHARGE PUMP OUTPUT
NORMAL
THREE-STATE
0
1
1
1
CE PIN PD2 PD1 MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
X
X
0
1
X
0
1
1
F5
X
0
1
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE2
F4
0
1
1
P1
0
1
0
1
PRESCALER VALUE
8/9
16/17
32/33
64/65
P2
0
0
1
1
CPI6
CPI3
CPI5
CPI2
CPI4
CPI1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I
CP
(mA)
2.7k 4.7k 10k
1.09
2.18
3.26
4.35
5.44
6.53
7.62
8.70
0.63
1.25
1.88
2.50
3.13
3.75
4.38
5.00
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
CURRENT
SETTTING
2
DB23 DB22
DB21
DB20 DB19 DB18
DB17
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
DB6
DB5 DB4 DB3DB13
CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)F5
CONTROL
BITS
PRESCALER
VALUE
DB2 DB1
DB0
PD2P1 CPI3 CPI2
POWER-
DOWN 2
CURRENT
SETTTING
1
TIMER COUNTER
CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREE-
STATE
PD
POLARITY
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
P2
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
SEE PAGE 17
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