Low Phase Noise, Fast Settling PLL

Frequency Synthesizer

ADF4193

Rev. B

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FEATURES

New, fast settling, fractional-N PLL architecture

Single PLL replaces ping-pong synthesizers

Frequency hop across GSM band in 5 μs with phase settled

by 20 μs

0.5° rms phase error at 2 GHz RF output

Digitally programmable output phase

RF input range up to 3.5 GHz

3-wire serial interface

On-chip, low noise differential amplifier

Phase noise figure of merit: −216 dBc/Hz

Loop filter design possible using ADI SimPLL

APPLICATIONS

GSM/EDGE base stations

PHS base stations

Instrumentation and test equipment

GENERAL DESCRIPTION

The ADF4193 frequency synthesizer can be used to implement

local oscillators in the upconversion and downconversion

sections of wireless receivers and transmitters. Its architecture

is specifically designed to meet the GSM/EDGE lock time

requirements for base stations. It consists of a low noise, digital

phase frequency detector (PFD), and a precision differential

charge pump. There is also a differential amplifier to convert

the differential charge pump output to a single-ended voltage

for the external voltage-controlled oscillator (VCO).

The Σ-Δ based fractional interpolator, working with the N

divider, allows programmable modulus fractional-N division.

Additionally, the 4-bit reference (R) counter and on-chip

frequency doubler allow selectable reference signal (REFIN)

frequencies at the PFD input. A complete phase-locked loop

(PLL) can be implemented if the synthesizer is used with an

external loop filter and a VCO. The switching architecture

ensures that the PLL settles inside the GSM time slot guard

period, removing the need for a second PLL and associated

isolation switches. This decreases cost, complexity, PCB area,

shielding, and characterization on previous ping-pong GSM

PLL architectures.

FUNCTIONAL BLOCK DIAGRAM

05328-001

N COUNTER

SW1

OUT+

OUT–

SW2

REFERENCE

DATA

24-BIT

DATA

CLK

REF

GND

1 A

GND

2 D

GND

1 D

GND

2 D

GND

3 SD

GND

DGND

LOCK DETECT

DIV

SDV

1 DV

2 DV

SET

OUTPUT

MUX

OUT

–

HIGH Z

PHASE

FREQUENCY

DETECTOR

ADF4193

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

IN+

IN–

×2

DOUBLER

4-BIT R

COUNTER

DIVIDER

CHARGE

PUMP

–

DIFFERENTIAL

AMPLIFIER

CMR

AIN–

AIN+

OUT

SW3

Figure 1.

ADF4193

Rev. B | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

Reference Input Section............................................................. 11

RF Input Stage............................................................................. 11

FRAC/INT Register (R0)........................................................... 15

MOD/R Register (R1)................................................................ 16

Phase Register (R2) .................................................................... 17

Function Register (R3) .............................................................. 18

Charge Pump Register (R4) ...................................................... 19

Power-Down Register (R5)....................................................... 20

Mux Register (R6) ...................................................................... 21

Programming .................................................................................. 22

Worked Example ........................................................................ 22

Spur Mechanisms ....................................................................... 22

Power-Up Initialization ............................................................. 23

Changing the Frequency of the PLL and the Phase Look-Up

Table ............................................................................................. 23

Applications..................................................................................... 25

Local Oscillator for A GSM Base Station................................ 25

Interfacing ................................................................................... 27

PCB Design Guidelines for Chip Scale Package .................... 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

6/06—Rev A. to Rev. B

Changes to Table 1............................................................................ 3

Changes to Figure 32...................................................................... 18

Changes to Power-Up Initialization Section............................... 23

Changes to Timer Values for Tx Section and Timer Values for

Rx Section........................................................................................ 25

11/05—Rev 0. to Rev. A

Updated Format..................................................................Universal

Changes to Features Section............................................................ 1

Changes to Table 1............................................................................ 3

Changes to Reference Input Section ............................................ 11

Changes to RF N Divider Section ................................................ 11

Changes to the Lock Detect Section ............................................ 13

Changes to Figure 29...................................................................... 15

Changes to the 8-Bit INT Value Section ..................................... 15

Changes to Figure 33...................................................................... 19

Replaced Figure 35 ......................................................................... 21

Changes to the Σ-Δ and Lock Detect Modes Section................ 21

Changes to the Power-Up Initialization Section........................ 23

Changes to Table 8.......................................................................... 23

Changes to the Local Oscillator for a GSM

Base Station Section ....................................................................... 25

Changes to the Timer Values for Rx Section .............................. 25

Changes to Figure 36...................................................................... 26

Updates to the Outline Dimensions ............................................ 28

Changes to the Ordering Guide ................................................... 28

4/05—Revision 0: Initial Version

ADF4193

Rev. B | Page 3 of 28

SPECIFICATIONS

= DV

= SDV

= 3 V ± 10%, V

1, V

2 = 5 V ± 10%, V

3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, R

SET

= 2.4 kΩ, dBm

referred to 50 Ω, T

= T

MIN

to T

MAX

, unless otherwise noted.

Table 1.

Parameter B Version

Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RF

) 0.4/3.5 GHz min/max See Figure 21 for input circuit

RF Input Sensitivity –10/0 dBm min/max

Maximum Allowable Prescaler Output Frequency

470 MHz max

REF

CHARACTERISTICS

REF

Input Frequency 300 MHz max For f > 120 MHz, set REF/2 bit = 1

REF

Edge Slew Rate 300 V/μs min

REF

Input Sensitivity 0.7/V

V p-p min/max AC-coupled

0 to V

V max CMOS-compatible

REF

Input Capacitance 10 pF max

REF

Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency 26 MHz max

CHARGE PUMP

Up/Down

High Value 6.6 mA typ With R

SET

= 2.4 kΩ

Low Value 104 μA typ With R

SET

= 2.4 kΩ

Absolute Accuracy 5 % typ

SET

Range 1/4 kΩ min/max Nominally R

SET

= 2.4 kΩ

Three-State Leakage 1 nA typ

Up vs. Down Matching 0.1 % typ 0.75 V ≤ V

≤ V

– 1.5 V

vs. V

1 % typ 0.75 V ≤ V

≤ V

– 1.5 V

vs. Temperature 1 % typ 0.75 V ≤ V

≤ V

– 1.5 V

DIFFERENTIAL AMPLIFIER

Input Current 1 nA typ

Output Voltage Range 1.4/(V

3 − 0.3) V min/max

VCO Tuning Range 1.8/(V

3 − 0.8) V min/max

Output Noise 7 nV/√Hz typ @ 20 kHz offset

LOGIC INPUTS

, Input High Voltage 1.4 V min

, Input Low Voltage 0.7 V max

INH

, I

INL

, Input Current ±1 μA max

, Input Capacitance 10 pF max

LOGIC OUTPUTS

, Output High Voltage V

– 0.4 V min I

= 500 μA

, Output Low Voltage 0.4 V max I

= 500 μA

POWER SUPPLIES

2.7/3.3 V min/V max

1, V

2 4.5/5.5 V min/V max AV

≤ V

1, V

2 ≤ 5.5 V

3 5.0/5.65 V min/V max V

1, V

2 ≤ V

3 ≤ 5.65 V

(AV

+ DV

+ SDV

) 27 mA max 22 mA typ

1 + V

2) 27 mA max 22 mA typ

3) 30 mA max 24 mA typ

Power-Down 10 μA typ

Part #	ADF4193BCPZ
Description	PLL FREQ SYNTHESIZER SGL 32LFCSP EP - Trays
Category	IC
Availability	In Stock
Qty	5

ADF4193BCPZ

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