REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

ADF4106

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

PLL Frequency Synthesizer

FEATURES

6.0 GHz Bandwidth

2.7 V to 3.3 V Power Supply

Separate Charge Pump Supply (V

) Allows Extended

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

Programmable Anti-Backlash Pulsewidth

3-Wire Serial Interface

Analog and Digital Lock Detect

Hardware and Software Power-Down Mode

APPLICATIONS

Broadband Wireless Access

Instrumentation

Wireless LANS

Base Stations For Wireless Radio

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

AB COUNTER

LATCH

24-BIT INPUT

REF

CLK

DATA

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

REFERENCE

CPGND

SET

CURRENT

SETTING 2

CURRENT

SETTING 1

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

LOCK

DETECT

MUXOUT

OUT

HIGH Z

13-BIT

B COUNTER

PRESCALER

P/P + 1

6-BIT

A COUNTER

FROM

FUNCTION

LATCH

LOAD

M3 M2 M1

MUX

N = BP + A

AGND

DGND

ADF4106

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement

local oscillators in the up-conversion and down-conversion

sections of wireless receivers and transmitters. It consists of a

low-noise digital PFD (Phase Frequency Detector), a precision

charge pump, a programmable reference divider, programmable

A and B counters and a dual-modulus prescaler (P/P + 1). The

A (6-bit) and B (13-bit) counters, in conjunction with the dual

modulus prescaler (P/P + 1), implement an N divider (N = BP + A).

In addition, the 14-bit reference counter (R Counter), allows

selectable REFIN frequencies at the PFD input. A complete

PLL (Phase-Locked Loop) can be implemented if the synthe-

sizer is used with an external loop filter and VCO (Voltage

Controlled Oscillator). Its very high bandwidth means that

frequency doublers can be eliminated in many high-frequency

systems, simplifying system architecture and lowering cost.

REV. 0

–2–

ADF4106–SPECIFICATIONS

BChips

Parameter B Version

(typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 3 for Input Circuit

RF Input Frequency (RF

)

0.5/6.0 0.5/6.0 GHz min/max

RF Input Sensitivity –10/0 –10/0 dBm min/max

Maximum Allowable

Prescaler Output Frequency

300 300 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-Coupled

Square Wave, (0 to V

)

REFIN Input Sensitivity

0.8/AV

V p-p min/max AC-Coupled; When DC-Coupled,

0 to V

max (CMOS Compatible)

REFIN Input Capacitance 10 10 pF max

REFIN Input Current ± 100 ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

56 56 MHz max

CHARGE PUMP

Sink/Source Programmable, See Table V

High Value 5 5 mA typ With R

SET

= 5.1 kΩ

Low Value 625 625 µA typ

Absolute Accuracy 2.5 2.5 % typ With R

SET

= 5.1 kΩ

SET

Range 2.7/10 2.7/10 kΩ typ See Table V

Three-State Leakage Current 1 1 nA typ

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. V

1.5 1.5 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. Temperature 2 2 % typ V

= V

LOGIC INPUTS

INH

, Input High Voltage 1.4 1.4 V min

INL

, Input Low Voltage 0.6 0.6 V max

INH

INL

, Input Current ± 1 ± 1 µA max

, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

, Output High Voltage 1.4 1.4 V min Open Drain Output Chosen 1 kΩ

Pull-up to 1.8 V

, Output High Voltage 1.4 1.4 V min CMOS Output Chosen

100 100 µA max

, Output Low Voltage 0.4 0.4 V max I

= 500 µA

POWER SUPPLIES

2.7/3.3 2.7/3.3 V min/V max

/5.5 AV

/5.5 V min/V max AV

ⱕ V

ⱕ 5.5 V

(AI

+ DI

) 15 13 mA max 13 mA typ

0.4 0.4 mA max T

= 25°C

Power-Down Mode

(AI

+ DI

)10 10 µA typ

(AV

= DV

= 3 V  10%; AV

≤ V

≤ 5.5 V; AGND = DGND = CPGND = 0 V;

SET

= 5.1 k; dBm referred to 50 ; T

= T

MIN

to T

MAX

unless otherwise noted.)

–3–

REV. 0

BChips

Parameter B Version

(typ) Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Phase Noise Floor

–174 –174 dBc/Hz typ @ 25 kHz PFD Frequency

–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency

–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency

Phase Noise Performance

@ VCO Output

900 MHz Output

–93 –93 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–74 –74 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–84 –84 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

Spurious Signals

900 MHz Output

–90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency

NOTES

Operating temperature range (B Version) is –40°C to +85°C.

The BChip specifications are given as typical values.

Use a square wave for lower frequencies, below the mimimum stated.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

= DV

= 3 V

Guaranteed by design. Sample tested to ensure compliance.

= 25°C; AV

= DV

= 3 V; P = 16; RF

= 6.0 GHz

= 25°C; AV

= DV

= 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF

= 6.0 GHz

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (f

REFOUT

= 10 MHz @ 0 dBm).

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset Frequency = 1 kHz; f

= 900 MHz; N = 4500; Loop B/W = 20 kHz

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset Frequency = 1 kHz; f

= 5800 MHz; N = 29000; Loop B/W = 20 kHz

REFIN

= 10 MHz; f

PFD

= 1 MHz; Offset Frequency = 1 kHz; f

= 5800 MHz; N = 5800; Loop B/W = 100 kHz

Specifications subject to change without notice.

(AV

= DV

= 3 V  10%; AV

≤ V

≤ 5.5 V; AGND = DGND = CPGND = 0 V; R

SET

= 5.1 k;

= T

MIN

to T

MAX

unless otherwise noted.)

CLOCK

DB23 (MSB)

DB22

DB2

DB1 (CONTROL

BIT C2)

DATA

DB0 (LSB)

(CONTROL BIT C1)

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

Limit at

MIN

to T

MAX

Parameter (B Version) Unit Test Conditions/Comments

10 ns min DATA to CLOCK Setup Time

10 ns min DATA to CLOCK Hold Time

25 ns min CLOCK High Duration

25 ns min CLOCK Low Duration

10 ns min CLOCK to LE Setup Time

20 ns min LE Pulsewidth

Guaranteed by design but not production tested.

ADF4106

Part #	ADF4106BCP
Description	Clock Generator 20MHz to 6GHzInput 325MHz Output 20-Pin L
Category	IC
Availability	In Stock
Qty	24

Qty	Price
1 - 5	$4.47726
6 - 10	$3.56145
11 - 15	$3.35794
16 - 20	$3.12051
21 +	$2.78133

ADF4106BCP

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