REV. 0
ADF4106
–15–
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock under the control of the Timer Counter. After the
timeout period determined by the value in TC4–TC1, the CP
Gain bit in the AB counter latch is automatically reset to “0”
and the device reverts to normal mode instead of Fastlock. See
Table V for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump cur-
rents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in a
state of change (i.e., when a new output frequency is programmed).
The normal sequence of events is as follows:
Users initially decide what the preferred charge pump currents
are will be. For example, they may choose 2.5 mA as Current
Setting 1 and 5 mA as the Current Setting 2. At the same time
they must also decide how long they want the secondary cur-
rent to stay active before reverting to the primary current. This
is controlled by the Timer Counter Control Bits DB14 to
DB11 (TC4–TC1) in the Function Latch. The truth table is
given in Table V.
Now, when users wish to program a new output frequency, they
can simply program the AB counter latch with new values for A
and B. At the same time they can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3–CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time that the user wishes
to change the frequency again.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
Prescaler Value
P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not valid.
PD Polarity
This bit sets the Phase Detector Polarity Bit. See Table V.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
THE FUNCTION LATCH
With C2, C1 set to 1,0, the on-chip function latch will be
programmed. Table V shows the input data format for program-
ming the Function Latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A,B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled
(set to “0”). The N counter then resumes counting in “close” align-
ment with the R counter. (The maximum error is one prescaler cycle).
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide
programmable power-down modes. They are enabled by the CE
pin. When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1. In the programmed asyn-
chronous power-down, the device powers down immediately
after latching a “1” into bit PD1, with the condition that PD2
has been loaded with a “0.” In the programmed synchronous
power-down, the device power down is gated by the charge
pump to prevent unwanted frequency jumps. Once the power-
down is enabled by writing a “1” into bit PD1 (on condition
that a “1” has also been loaded to PD2), then the device will go
into power-down on the occurrence of the next charge pump
event. When a power down is activated (either synchronous or
asynchronous mode including CE-pin-activated power down),
the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF
IN
input is debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 Family. Table V shows the truth table.
Fastlock Enable Bit
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
Fastlock Mode Bit
DB10 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “ 0,” Fastlock Mode 1 is
selected and if the Fastlock Mode bit is “1,” Fastlock Mode 2 is
selected.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock by having a “0” written to the CP Gain bit in the AB
counter latch.
