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ADF4112BRU

Part # ADF4112BRU
Description PLL FREQ SYNTHESIZER SGL 16TSSOP - Rail/Tube
Category IC
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Analog Devices
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the
ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
AV
DD
to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θ
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θ
JA
Thermal Impedance (Paddle Soldered) . . . 122°C/W
CSP θ
JA
Thermal Impedance
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
ORDERING GUIDE
Model Temperature Range Package Description Package Option*
ADF4110BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4110BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4111BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4111BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4112BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4112BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4113BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BCHIPS –40°C to +85°C DICE DICE
*Contact the factory for chip availability.
CLOCK
DATA
LE
LE
DB20 (MSB) DB19 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
t
5
t
1
t
2
t
3
t
4
Figure 1. Timing Diagram
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
5
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.56 V. The relationship between I
CP
and R
SET
is
I
R
CP
SET
max
.
=
23 5
So, with R
SET
= 4.7 k, I
CPmax
= 5 mA.
2 CP Charge Pump Output. When enabled this provides ± I
CP
to the external loop filter, which in turn drives the
external VCO.
3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the prescaler.
5RF
IN
B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 25.
6RF
IN
A Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7AV
DD
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resis-
tance of 100 k. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9 DGND Digital Ground.
10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA Serial Data Input. The serial data is loaded MSB rst with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
15 DV
DD
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
16 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R
SET
V
P
ADF4110
ADF4111
ADF4112
ADF4113
CP
DV
DD
CPGND
MUXOUT
AGND
LE
RF
IN
B
DATA
RF
IN
A
CLK
AV
DD
CE
REF
IN
DGND
CHIP SCALE PACKAGE
TOP VIEW
(Not to Scale)
CPGND
AGND
AGND
RF
IN
B
RF
IN
A
MUXOUT
LE
DATA
CLK
CE
ADF4110
ADF4111
ADF4112
ADF4113
CP
R
SET
V
P
DV
DD
DV
DD
AV
DD
AV
DD
REF
IN
DGND
DGND
1
2
3
4
5
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
6
Typical Performance Characteristics
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
GHz S MA R 50
FREQ MAGS11 ANGS11
1.05 0.9512 –40.134
1.10 0.93458 –43.747
1.15 0.94782 –44.393
1.20 0.96875 –46.937
1.25 0.92216 –49.6
1.30 0.93755 –51.884
1.35 0.96178 –51.21
1.40 0.94354 –53.55
1.45 0.95189 –56.786
1.50 0.97647 –58.781
1.55 0.98619 –60.545
1.60 0.95459 –61.43
1.65 0.97945 –61.241
1.70 0.98864 –64.051
1.75 0.97399 –66.19
1.80 0.97216 –63.775
FREQ MAGS11 ANGS11
0.05 0.89207 –2.0571
0.10 0.8886 –4.4427
0.15 0.89022 –6.3212
0.20 0.96323 –2.1393
0.25 0.90566 –12.13
0.30 0.90307 –13.52
0.35 0.89318 –15.746
0.40 0.89806 –18.056
0.45 0.89565 –19.693
0.50 0.88538 –22.246
0.55 0.89699 –24.336
0.60 0.89927 –25.948
0.65 0.87797 –28.457
0.70 0.90765 –29.735
0.75 0.88526 –31.879
0.80 0.81267 –32.681
0.85 0.90357 –31.522
0.90 0.92954 –34.222
0.95 0.92087 –36.961
1.00 0.93788 –39.343
Figure 2. S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)
RF INPUT FREQUENCY GHz
0
4
2
3
35
RF INPUT POWER dBm
0
15
20
25
30
5
10
1
V
DD
= 3V
V
P
= 3V
T
A
= +85C
T
A
= +25C
T
A
= 40C
5
Figure 3. Input Sensitivity (ADF4113)
2kHz 1kHz 900MHz +1kHz +2kHz
V
DD
= 3V, V
P
= 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
91.0dBc/Hz
REFERENCE
LEVEL = 4.2dBm
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
Figure 4. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
2kHz 1kHz 900MHz +1kHz +2kHz
V
DD
= 3V, V
P
= 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
REFERENCE
LEVEL = 4.2dBm
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
92.5dBc/Hz
Figure 5. ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.52
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
0.52 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
Figure 6. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400
µ
s)
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.62
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
0.62 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
Figure 7. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200
µ
s)
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