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AD8361-ARM

Part # AD8361-ARM
Description
Category IC
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Analog Devices
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD8361
–10–
REV. A
With the 100 pF capacitor shown in Figures 3234, the high-
pass corner frequency is about 8 MHz.
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
45
6
7
8
0.01F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 32. Basic Connections for Ground Referenced Mode
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
45
6
7
8
0.01F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 33. Basic Connections for Internal Reference Mode
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
45
6
7
8
0.01F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 34. Basic Connections for Supply Referenced Mode
The output voltage is nominally 7.5 times the input rms voltage
(a conversion gain of 7.5 V/V rms). Three different modes of
operation are set by the pins SREF and IREF. In addition to the
ground referenced mode shown in Figure 32, where the output
voltage swings from around near ground to 4.9 V on a 5.0 V
supply, two additional modes allow an offset voltage to be added to
the output. In the internal reference mode, (Figure 33), the
output voltage swing is shifted upward by an internal reference
voltage of 350 mV. In supply referenced mode (Figure 34), an
offset voltage of V
S
/7.5 is added to the output voltage. Table I
summarizes the connections, output transfer function and mini-
mum output voltage (i.e., zero signal) for each mode.
Output Swing
Figure 35 shows the output swing of the AD8361 for a 5 V supply
voltage for each of the three modes. It is clear from Figure 35,
that operating the device in either internal reference mode or
supply referenced mode, will reduce the effective dynamic range as
the output headroom decreases. The response for lower supply
voltages is similar (in the supply referenced mode, the offset is
smaller), but the dynamic range will be reduced further, as head-
room decreases. Figure 36 shows the response of the AD8361 to
a CW input for various supply voltages.
INPUT V rms
5.0
4.5
0.0
0
0.50.1 0.2 0.3 0.4
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
OUTPUT Volts
SUPPLY REF
INTERNAL REF
GROUND REF
0.6 0.7 0.8
Figure 35. Output Swing for Ground, Internal and Supply
Referenced Mode. VPOS = 5 V (micro_SOIC Only)
INPUT V rms
5.5
1.5
0
0.50.1 0.2 0.3 0.4
4.0
3.0
2.5
2.0
5.0
4.5
3.5
OUTPUT Volts
1.0
0.5
0.0
5.5V
5.0V
3.0V
2.7V
0.6 0.7 0.8
Figure 36. Output Swing for Supply Voltages of 2.7 V,
3.0 V, 5.0 V and 5.5 V (micro_SOIC Only)
Dynamic Range
Because the AD8361 is a linear responding device with a nomi-
nal transfer function of 7.5 V/V rms, the dynamic range in dB is
not clear from plots such as Figure 35. As the input level is
increased in constant dB steps, the output step size (per dB)
will also increase. Figure 37 shows the relationship between the
output step size (i.e., mV/dB) and input voltage for a nominal
transfer function of 7.5 V/V rms.
Table I. Connections and Nominal Transfer Function for
Ground, Internal, and Supply Reference Modes
Output
Reference Intercept
Mode IREF SREF (No Signal) Output
Ground VPOS COMM Zero 7.5 V
IN
Internal OPEN COMM 0.350 V 7.5 V
IN
+ 0.350 V
Supply VPOS VPOS V
S
/7.5 7.5 V
IN
+ V
S
/7.5
AD8361
–11–
REV. A
INPUT mV
700
200
0
500100 200 300 400
500
400
300
600
mV/dB
100
0
600 700 800
Figure 37. Idealized Output Step Size as Function of Input
Voltage
Plots of output voltage vs. input voltage result in a straight line. It
may sometimes be more useful to plot the error on a logarith-
mic scale, as shown in Figure 38. The deviation of the plot for
the ideal straight line characteristic is caused by output clipping
at the high end and by signal offsets at the low end. It should
however be noted that offsets at the low end can be either posi-
tive or negative, so that this plot could also trend upwards at the
low end. Figures 5, 6, 8, and 9 show a ±3 sigma distribution of
device error for a large population of devices.
INPUT V rms
2.0
0.5
0.01
0.5
0.0
1.5
1.0
ERROR dB
1.0
1.5
2.0
1.0
1.9GHz
2.5GHz
900MHz
100MHz
100MHz
0.02
(21dBm)
0.1
(7dBm)
0.4
(+5dBm)
Figure 38. Representative Unit, Error in dB vs. Input Level,
V
S
= 2.7 V
It is also apparent in Figure 38 that the error plot tends to
shift to the right with increasing frequency. Because the input
impedance decreases with frequency, the voltage actually applied
to the input will also tend to decrease (assuming a constant source
impedance over frequency). The dynamic range is almost con-
stant over frequency, but with a small decrease in conversion gain
at high frequency.
Input Coupling and Matching
The input impedance of the AD8361 decreases with increasing
frequency in both its resistive and capacitive components (Figure
13). The resistive component varies from 225 at 100 MHz
down to about 95 at 2.5 GHz.
A number of options exist for input matching. For operation at
multiple frequencies, a 75 shunt to ground, as shown in Figure
39a, will provide the best overall match. For use at a single fre-
quency, a resistive or a reactive match can be used. By plotting the
input impedance on a Smith Chart, the best value for a
resistive match can be calculated. The VSWR can be held below
1.5 at frequencies up to 1 GHz, even as the input impedance
varies from part to part. (Both input impedance and input
capacitance can vary by up to ±20% around their nominal values.)
At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt
resistor will not be sufcient to reduce the VSWR below 1.5.
Where VSWR is critical, remove shunt component and insert
an inductor in series with the coupling capacitor as shown in
Figure 39b.
Table II gives recommended shunt resistor values for various
frequencies and series inductor values for high frequencies. The
coupling capacitor, C
C
, essentially acts as an ac-short and plays
no intentional part in the matching.
AD8361
RFIN
RFIN
R
SH
C
C
a. Broadband Resistor Match
AD8361
C
C
RFIN
RFIN
L
M
b. Series Inductor Match
AD8361
C
C
RFIN
RFIN
L
M
C
M
c. Narrowband Reactive Match
AD8361
C
C
RFIN
RFIN
R
SERIES
d. Attenuating the Input Signal
Figure 39. Input Coupling/Matching Options
Table II. Recommended Component Values for Resistive or
Inductive Input Matching (Figures 39a and 39b)
Frequency Matching Component
100 MHz 63.4 Shunt
800 MHz 75 Shunt
900 MHz 75 Shunt
1800 MHz 150 Shunt or 4.7 nH Series
1900 MHz 150 Shunt or 4.7 nH Series
2500 MHz 150 Shunt or 2.7 nH Series
AD8361
–12–
REV. A
Alternatively, a reactive match can be implemented using a shunt
inductor to ground and a series capacitor as shown in Figure
39c. A method for hand calculating the appropriate matching
components is shown on page 12 of the AD8306 data sheet.
Matching in this manner results in very small values for C
M
,
especially at high frequencies. As a result, a stray capacitance as
small as 1 pF can signicantly degrade the quality of the match.
The main advantage of a reactive match is the increase in sensi-
tivity that results from the input voltage being gained up (by
the square root of the impedance ratio) by the matching network.
Table III shows recommended values for reactive matching.
Table III. Recommended Values for a Reactive Input Match
(Figure 39c)
Frequency C
M
L
M
MHz pF nH
100 16 180
800 2 15
900 2 12
1800 1.5 4.7
1900 1.5 4.7
2500 1.5 3.3
Input Coupling Using a Series Resistor
Figure 39d shows a technique for coupling the input signal
into the AD8361, which may be applicable where the input signal
is much larger than the input range of the AD8361. A series
resistor combines with the input impedance of the AD8361 to
attenuate the input signal. Since this series resistor forms a
divider with the frequency-dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped
off in RF power transmission applications. If the resistor is large
compared to the transmission lines impedance then the VSWR of
the system is relatively unaffected.
FREQUENCY MHz
200
0
500
RESISTANCE
100
0
250
150
50
1000 1500 2000 2500 3000 3500
0.2
0.5
0.8
1.1
1.4
1.7
CAPACITANCE pF
Figure 40. Input Impedance vs. Frequency, Supply 3 V,
SOT-23-6L
Selecting the Filter Capacitor
The AD8361s internal 27 pF lter capacitor is connected in
parallel with an internal resistance that varies with signal level
from 2 k for small signals to 500 for large signals. The
resulting low-pass corner frequency between 3 MHz and 12 MHz
provides adequate ltering for all frequencies above 240 MHz
(i.e., ten times the frequency at the output of the squarer, which
is twice the input frequency). However, signals with high peak-
to-average ratios, such as CDMA or W-CDMA signals, and
with low frequency components, require additional ltering.
TDMA signals, such as GSM, PDC, or PHS have a peak-to-
average ratio that is close to that of a sinusoid, and the internal
lter is adequate.
The lter capacitance of the AD8361 can be augmented by
connecting a capacitor between Pin 6 (FLTR) and VPOS.
Table IV shows the effect of several capacitor values for various
communications standards with high peak-to-average ratios along
with the residual ripple at the output, in peak-to-peak and rms
volts. Note that large lter capacitors will increase the enable
and pulse response times, as discussed below.
Table IV. Effect of Waveform and C
FILT
on Residual AC
Output Residual AC
Waveform C
FILT
V dc mV p-p mV rms
IS95 Reverse Link Open 0.5 550 100
1.0 1000 180
2.0 2000 360
0.01 µF 0.5 40 6
1.0 160 20
2.0 430 60
0.1 µF 0.5 20 3
1.0 40 6
2.0 110 18
IS95 8-Channel 0.01 µF 0.5 290 40
Forward Link 1.0 975 150
2.0 2600 430
0.1 µF 0.5 50 7
1.0 190 30
2.0 670 95
W-CDMA 15 0.01 µF 0.5 225 35
Channel 1.0 940 135
2.0 2500 390
0.1 µF 0.5 45 6
1.0 165 25
2.0 550 80
Operation at Low Frequencies
Although the AD8361 is specied for operation up to 2.5 GHz,
there is no lower limit on the operating frequency. It is only nec-
essary to increase the input coupling capacitor to reduce the
corner frequency of the input high-pass lter (use an input resis-
tance of 225 for frequencies below 100 MHz). It is also
necessary to increase the lter capacitor so that the signal at the
output of the squaring circuit is free of ripple. The corner fre-
quency will be set by the combination of the internal resistance of
2 k and the external lter capacitance.
Power Consumption, Enable and Power-On
The quiescent current consumption of the AD8361 varies with
the size of the input signal from about 1 mA for no signal up to
7 mA at an input level of 0.66 V rms (9.4 dBm re 50 ). If the
input is driven beyond this point, the supply current increases
steeply (see Figure 12). There is little variation in quiescent
current with power supply voltage.
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