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AD8361-ARM

Part # AD8361-ARM
Description
Category IC
Availability In Stock
Qty 14
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9 - 11 $10.66838
12 + $9.50878
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Analog Devices
Date Code: 0022
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD8361
–7–
REV. A
67mV
370mV
270mV
25mV
5s PER HORIZONTAL DIVISION
GATE PULSE FOR
900MHz RF TONE
RF INPUT
500mV PER
VERTICAL
DIVISION
Figure 20. Output Response to Modulated Pulse Input
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, No Filter Capacitor
67mV
370mV
25mV
500mV PER
VERTICAL
DIVISION
50s PER HORIZONTAL DIVISION
RF INPUT
GATE PULSE FOR
900MHz RF TONE
270mV
Figure 21. Output Response to Modulated Pulse Input
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, 0.01
µ
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
HPE3631A
POWER SUPPLY
C4
0.01F
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
0.1F
R1
75
C3
TEK TDS784C
SCOPE
C5
100pF
TEK P6204
FET PROBE
Figure 22. Hardware Configuration for Output Response
to Modulated Pulse Input
RF INPUT
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
2s PER HORIZONTAL DIVISION
Figure 23. Output Response Using Power-Down Mode
for Various RF Input Levels, Supply 3 V, Frequency
900 MHz, No Filter Capacitor
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
20s PER HORIZONTAL DIVISION
RF INPUT
Figure 24. Output Response Using Power-Down Mode
for Various RF Input Levels, Supply 3 V, Frequency
900 MHz, 0.01
µ
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
HPE3631A
POWER SUPPLY
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
0.1F
R1
75
C3
HP8110A
PULSE
GENERATOR
C4
0.01F
C5
100pF
TEK P6204
FET PROBE
TEK TDS784C
SCOPE
Figure 25. Hardware Configuration for Output Response
Using Power-Down Mode
AD8361
–8–
REV. A
CARRIER FREQUENCY MHz
7.8
7.6
6.2
100 1000
7.2
6.6
6.4
7.4
6.8
7.0
CONVERSION GAIN V/V rms
6.0
5.8
5.6
V
S
= 3V
Figure 26. Conversion Gain Change vs. Frequency, Supply
3 V, Ground Reference Mode, Frequency 100 MHz to
2500 MHz, Representative Device
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
SUPPLY
20s PER HORIZONTAL DIVISION
RF
INPUT
Figure 27. Output Response to Gating On Power Supply,
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, 0.01
µ
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
R1
75
HP8110A
PULSE
GENERATOR
50
732
C4
0.01F
AD811
C5
100pF
TEK P6204
FET PROBE
TEK TDS784C
SCOPE
C3
0.1F
Figure 28. Hardware Configuration for Output Response
to Power Supply Gating Measurements
CONVERSION GAIN V/V rms
7.66.9 7.0 7.2
16
PERCENT
7.4 7.8
14
12
10
8
6
4
2
0
Figure 29. Conversion Gain Distribution Frequency
100 MHz, Supply 5 V, Sample Size 3000
IREF MODE INTERCEPT Volts
0.400.32 0.34 0.36
PERCENT
0.38 0.44
12
10
8
6
4
2
0
0.42
12
Figure 30. Output Reference, Internal Reference Mode,
Supply 5 V, Sample Size 3000 (micro_SOIC Only)
SREF MODE INTERCEPT Volts
0.720.64 0.66 0.68
PERCENT
0.70 0.76
12
10
8
6
4
2
0
0.74
12
12
Figure 31. Output Reference, Supply Reference Mode,
Supply 5 V, Sample Size 3000 (micro_SOIC Only)
AD8361
–9–
REV. A
CIRCUIT DESCRIPTION
The AD8361 is an rms-responding (mean power) detector pro-
viding an approach to the exact measurement of RF power that
is basically independent of waveform. It achieves this function
through the use of a proprietary technique in which the outputs
of two identical squaring cells are balanced by the action of a
high-gain error amplier.
The signal to be measured is applied to the input of the rst
squaring cell, which presents a nominal (LF) resistance of 225
between the pin RFIN and COMM (connected to the ground
plane). Since the input pin is at a bias voltage of about 0.8 V
above ground, a coupling capacitor is required. By making this
an external component, the measurement range may be extended
to arbitrarily low frequencies.
The AD8361 responds to the voltage, V
IN
, at its input, by squaring
this voltage to generate a current proportional to V
IN
squared.
This is applied to an internal load resistor, across which is con-
nected a capacitor. These form a low-pass lter, which extracts
the mean of V
IN
squared. Although essentially voltage-responding,
the associated input impedance calibrates this port in terms of
equivalent power. Thus 1 mW corresponds to a voltage input of
447 mV rms. In the Application section it is shown how to match
this input to 50 .
The voltage across the low-pass lter, whose frequency may
be arbitrarily low, is applied to one input of an error-sensing
amplier. A second identical voltage-squaring cell is used to
close a negative feedback loop around this error amplier.
This second cell is driven by a fraction of the quasi-dc output
voltage of the AD8361. When the voltage at the input of the
second squaring cell is equal to the rms value of V
IN
, the loop
is in a stable state, and the output then represents the rms value of
the input. The feedback ratio is nominally 0.133, making the
rms-dc conversion gain ×7.5, that is
V
OUT
= 7.5 × V
IN
rms
By completing the feedback path through a second squaring cell,
identical to the one receiving the signal to be measured, several
benets arise. First, scaling effects in these cells cancel; thus, the
overall calibration may be accurate, even though the open-loop
response of the squaring cells taken separately need not be.
Note that in implementing rms-dc conversion, no reference
voltage enters into the closed-loop scaling. Second, the tracking
in the responses of the dual cells remains very close over tempera-
ture, leading to excellent stability of calibration.
The squaring cells have very wide bandwidth with an intrinsic
response from dc to microwave. However, the dynamic range
of such a system is fairly small, due in part to the much larger
dynamic range at the output of the squaring cells. There are
practical limitations to the accuracy with which very small error
signals can be sensed at the bottom end of the dynamic range,
arising from small random offsets; these set the limit to the
attainable accuracy at small inputs.
On the other hand, the squaring cells in the AD8361 have
a Class-AB aspect; the peak input is not limited by their
quiescent bias condition, but is determined mainly by the
eventual loss of square-law conformance. Consequently, the top
end of their response range occurs at a fairly large input level
(about 700 mV rms) while preserving a reasonably accurate
square-law response. The maximum usable range is, in practice,
limited by the output swing. The rail-to-rail output stage can
swing from a few millivolts above ground to less than 100 mV
below the supply. An example of the output induced limit: given
a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V
supply; the maximum input is (2.9 V rms)/7.5 or 390 mV rms.
Filtering
An important aspect of rms-dc conversion is the need for
averaging (the function is root-MEAN-square). For complex RF
waveforms such as occur in CDMA, the ltering provided by
the on-chip low-pass lter, while satisfactory for CW signals above
100 MHz, will be inadequate when the signal has modulation
components that extend down into the kilohertz region. For this
reason, the FLTR pin is provided: a capacitor attached between
this pin and VPOS can extend the averaging time to very low
frequencies.
Offset
An offset voltage can be added to the output (when using the
micro_SOIC version) to allow the use of A/D converters whose
range does not extend down to ground. However, accuracy at
the low end will be degraded because of the inherent error in this
added voltage. This requires that the pin IREF (internal reference)
should be tied to VPOS and SREF (supply reference) to ground.
In the IREF mode, the intercept is generated by an internal
reference cell, and is a xed 350 mV, independent of the supply
voltage. To enable this intercept, IREF should be open-circuited,
and SREF should be grounded.
In the SREF mode, the voltage is provided by the supply. To
implement this mode, tie IREF to VPOS and SREF to VPOS. The
offset is then proportional to the supply voltage, and is 400 mV
for a 3 V supply and 667 mV for a 5 V supply.
USING THE AD8361
Basic Connections
Figures 32, 33, and 34 show the basic connections for the
micro_SOIC version AD8361 in its three operating modes. In all
modes, the device is powered by a single supply of between 2.7 V
and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01 µF
capacitors. The quiescent current of 1.1 mA in operating mode
can be reduced to 1 µA by pulling the PWDN pin up to VPOS.
A 75 external shunt resistance combines with the ac-coupled
input to give an overall broadband input impedance near 50 .
Note that the coupling capacitor must be placed between the in-
put and the shunt impedance. Input impedance and input coupling
are discussed in more detail below.
The input coupling capacitor combines with the internal input
resistance (Figure 13) to give a high-pass corner frequency
given by the equation
f
CR
dB
CIN
3
1
2
=
××π
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