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UC2825N

Part # UC2825N
Description HIGH SPEED PWM CONT - Rail/Tube
Category IC
Availability In Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

4
UC1825
UC2825
UC3825
UC1825
UC3825
PARAMETERS TEST CONDITIONS UC2825
MIN TOP MAX MIN TOP MAX UNITS
PWM Comparator Section
Pin 7 Bias Current V
PIN 7 = 0V -1 -5 -1 -5 µA
Duty Cycle Range 0 80 0 85 %
Pin 3 Zero DC Threshold V
PIN 7 = 0V 1.1 1.25 1.1 1.25 V
Delay to Output* 50 80 50 80 ns
Soft-Start Section
Charge Current V
PIN 8 = 0.5V 3 9 20 3 9 20 µA
Discharge Current V
PIN 8 = 1V 1 1 mA
Current Limit / Shutdown Section
Pin 9 Bias Current 0 < V
PIN 9 < 4V 15 10 µA
Current Limit Threshold 0.9 1.0 1.1 0.9 1.0 1.1 V
Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V
Delay to Output 50 80 50 80 ns
Output Section
Output Low Level I
OUT = 20mA 0.25 0.40 0.25 0.40 V
I
OUT = 200mA 1.2 2.2 1.2 2.2 V
Output High Level I
OUT = -20mA 13.0 13.5 13.0 13.5 V
I
OUT = -200mA 12.0 13.0 12.0 13.0 V
Collector Leakage V
C = 30V 100 500 10 500 µA
Rise/Fall Time* CL = 1nF 30 60 30 60 ns
Under-Voltage Lockout Section
Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V
UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V
Supply Current Section
Start Up Current V
CC = 8V 1.1 2.5 1.1 2.5 mA
ICC V
PIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 22 33 22 33 mA
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.
5
UC1825
UC2825
UC3825
High speed circuits demand careful attention to layout
and component placement. To assure proper perfor
-
mance of the UC1825 follow these rules: 1) Use a ground
plane. 2) Damp or clamp parasitic inductive kick energy
from the gate of driven MOSFETs. Do not allow the out
-
put pins to ring below ground. A series gate resistor or a
shunt 1 Amp Schottky diode at the output pin will serve
this purpose. 3) Bypass V
CC,VC, and VREF. Use 0.1µF
monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1 cm of total lead length for
each capacitor between the bypassed pin and the ground
plane. 4) Treat the timing capacitor, CT, like a bypass ca
-
pacitor.
Open Loop Frequency Response Unity Gain Slew Rate
Simplified Schematic
Error Amplifier Circuit
PWM Applications
Conventional (Voltage Mode)
Current-Mode
Printed Circuit Board Layout Considerations
6
UC1825
UC2825
UC3825
Oscillator Circuit
Timing Resistance vs Frequency
80
100
120
140
160
10k 100k
470pF
1.0nF
1M
FREQ (Hz)
T (ns)
D
Deadtime vs Frequency
Synchronized Operation
Two Units in Close Proximity
Generalized Synchronization
µ
Deadtime vs C
T
(3k R
T
100k)
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