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UC2827DW-1

Part # UC2827DW-1
Description BUCK CUR/VOLT FED PUSH-PULL PWM CONT - Rail/Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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FEATURES DESCRIPTION
R
D
QS
20
DELAY
23
GND
11
VCC
REF
15
RT
17
CT
18
SYNC
19
CSA−
9
CSA+
8
SS
4
CSAO
7
CEA−
13
VEA−
16
VEA+
14
22
24
3
2
1
RAMPCEA+
12
CEAOVEAO
10
PULL
PGND
PUSH
SRC
BUCK
V+
DELAY
DELAY
T
Q
Q
REF
&
UVLO
SS
INHBT
UV
OSC
500 kHz
MAX
6 5
21
Current Sense
Amplifier
ILIM Comparator
+3 V
Current Error
Amplifier
PWM Comparator0.7 V
Flying
Driver
Push/Pull
Drivers
OSC
UVLO
Voltage Error
Amplifier
+
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365A APRIL 1999 REVISED AUGUST 2005
BUCK CURRENT/VOLTAGE FED PUSH-PULL
PWM CONTROLLERS
Ideal for Multiple Output and/or High
The UC3827 family of controller devices provides an
Voltage Output Voltage Converters
integrated control solution for cascaded buck and
push-pull converters. These converters are known as
Up to 500 kHz Operation
current fed or voltage fed push-pull converters and
High Voltage, High Current Floating
are ideally suited for multiple output and/or high
Driver for Buck Converter Stage
voltage output applications. In both current fed and
UC3827-1 Current Fed Controller has
voltage fed modes, the push-pull switches are driven
Push-Pull Drivers with Overlapping
at 50% nominal duty cycles and at one half the
switching frequency of the buck stage. In the current
Conduction Periods
fed mode, the two switches are driven with a speci-
UC3827-2 Voltage Fed Controller has
fied over-lap period to prevent ringing and voltage
Push-Pull Drivers with Nonoverlapping
stress on the devices. In the voltage fed mode, the
Conduction Periods
two switches are driven with a specified gap time
Average Current Mode, Peak Current
between the switches to prevent shorting the trans-
Mode or Voltage Mode with Input
former across the energy storage capacitor and to
prohibit excessive currents flowing through the de-
Voltage Feedforward Control for Buck
vices.
Power Stage
Wide Bandwidth, Low Offset,
The converter's output voltage is regulated by pulse
Differential Current Sense Amplifier
width modulation of the buck switch. The UC3827
contains complete protection and PWM control func-
Precise Short Circuit Current Control
tions for the buck converter. Easy control of the
floating switch is accomplished by the floating drive
circuitry. The gate drive waveform is level shifted to
support an input voltage up to 72 V
DC
.
BLOCK DIAGRAM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
DISSIPATION RATINGS
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365A APRIL 1999 REVISED AUGUST 2005
The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in
current mode control. Using current mode control prevents potential core saturation of the push-pull transformer
due to mismatches in timing and in component tolerances. With average current mode control, precise control of
the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak
current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage
regulation loop to assist only in fault conditions.
Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable
overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense
amplifier, and soft start circuitry.
ORDERING INFORMATION
(1)
PACKAGES
T
A
= T
J
PUSH-PULL TOPOLOGY
SOIC-24 PDIP-24 PLCC-28
Current Fed UC1827J-1 UC1827J-1
-55°C to 125°C
Voltage Fed UC1827J-2 UC1827J-2
Current Fed UC2827DW-1 UC2827N-1 -
-40°C to 85°C
Voltage Fed UC2827DW-2 UC2827N-2 -
Current Fed UC3827DW-1 UC3827N-1 UC3827Q-1
0°C to 70°C
Voltage Fed UC3827DW-2 UC3827N-2 -
(1) The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).
PACKAGE ( θ
JA
) JUNCTION-TO-AMBIENT ( θ
JC
) JUNCTION-TO-WHAT?
TEMPERATURE (°C/W) TEMPERATURE (°C/W)
24-pin (N) 60
(1)
30
24-pin (J) 70 to 90 28
(2)
28-pin (DW) 71 to 83
(3)
24
(3)
28-pin (QLCC) 40-65
(1)
30
(1) Specified θ
JA
(junction-to-ambient) refers to devices mounted to 5-in
2
FR4 PC board with 1 oz. copper where noted. When a resistance
range is given, the lower values refer to a 5-in
2
aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm
trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of
each trace.
(2) Specified θ
JC
(junction-to-what?) data values stated were derived from MIL-STD-1835B which states " The baseline values shown are
worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils
2
. For
device sizes greater than 14400 mils
2
use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid
array, 10 °C/W."
(3) Modeled data. If there is a value range given for θ
JA
, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher
value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.
2
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ABSOLUTE MAXIMUM RATINGS
(1)
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V+
BUCK
SRC
SS
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
GND
CEA+
PUSH
VCC
PULL
PGND
DELAY
SYNC
CT
RT
VEA−
REF
VEA+
CEA−
N, J OR DW PACKAGES
(TOP VIEW)
3 2 1
13 14
5
6
7
8
9
10
11
PGND
NC
NC
DELAY
SYNC
CT
RT
SS
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
4
15 16 17 18
CEA+
CEA−
VEA+
REF
NC
VEA−
SRC
BUCK
NC
V+
Q PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
GND
PUSH
VCC
PULL
NC − No internal connection
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365A APRIL 1999 REVISED AUGUST 2005
UC2827-1
UC2827-2
UNITS
UC3827-1
UC3827-2
Supply voltage, VCC 20
CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL,
–0.3 to 5
RAMP, RT, SS, SYNC, VEA+, VEAO,
V
Input voltage range
V+ and BUCK 90
SRC 90-VCC
I/O continuous ±250 mA
BUCK driver
I/O peak ±1 A
I/O continuous ±200 mA
PUSH/PULL driver
I/O peak ±0.8 A
Storage temperature –65 to 150
Junction temperature –55 to 150 °C
Lead temperature (soldering, 10 sec) 300
(1) Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of
databook for thermal limitations and considerations of packages.
PLCC-28 (Q PACKAGE)
(TOP VIEW)
DIL-24 (N or J, DW PACKAGES)
(TOP VIEW)
3
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