V
OUT
ǒ
t
Ǔ
+ V
OUT,SET
ǒ
1 * e
*
t
RC
Ǔ
T
90%
+ 2.3 @ 480x10
3
@ C
SS3
(
mF
)
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Output Capacitor Selection (LDO)
A 2.2mF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with
any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or
lower ESR output capacitors can be used.
Soft-Start (LDO)
The LDO uses an external soft-start capacitor, C
SS3
, to provide an RC-ramped reference voltage to the control
loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the
current-controlled soft-start used by the buck controllers. The start-up waveform can be approximated by
Equation 14:
(14)
where R = 480 × 10
3
and C = capacitance in mF from SS3 to GND. The time taken to reach 90% of final V
OUT
can be approximated by Equation 15:
(15)
Setting Output Voltage (LDO)
Output voltage is set using two resistors as shown in Figure 1. Output voltage is then calculated using
Equation 16:
(16)
where V
FB
= 0.507V.
Internal Current Limit (LDO)
The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current
condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the
device. For good device reliability, the LDO should not operate at current limit.
Enable Pin (LDO)
The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start
capability are not required, EN3 can be tied to IN3.
Dropout Voltage (LDO)
The LDO uses a PMOS transistor to achieve low dropout. When (V
IN
– V
OUT
) is less than the dropout voltage
(V
DO
), the pass device is in its linear region of operation, and the input-output resistance is the R
DS,ON
of the pass
transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load
regulation degrade as (V
IN
– V
OUT
) falls much below 0.5V.
Transient Response (LDO)
The LDO does not have an on-chip pull-down circuit for output is over-voltage conditions. This feature permits
applications that connect higher voltage sources such as an alternate power supply to the output. This design
also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of
overshoot can be reduced by increasing C
OUT
; the duration of overshoot can be reduced by adding a load
resistor.
Thermal Protection (LDO)
Thermal protection disables the output when the junction temperature, T
J
, reaches unsafe levels. When the
junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the
regulator, protecting it from damage. For good long term reliability, the device should not be continuously
operated at or near thermal shutdown.
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