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TPS75301QPWPRQ1

Part # TPS75301QPWPRQ1
Description IC REG LDO ADJ 1.5A 20HTSSOP
Category IC
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Texas Instruments
Date Code: 0944
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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SGLS159A − APRIL 2003 − REVISED APRIL 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D 1.5-A Low-Dropout Voltage Regulator
D Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V, Fixed
Output and Adjustable Versions
D Open Drain Power-Good (PG) Status
Output (TPS751xxQ)
D Open Drain Power-On Reset With 100-ms
Delay (TPS753xxQ)
D Dropout Voltage Typically 160 mV at 1.5 A
(TPS75133Q)
D Ultralow 75 µA Typical Quiescent Current
D Fast Transient Response
D 2% Tolerance Over Specified Conditions
For Fixed-Output Versions
D 20-Pin TSSOP (PWP) PowerPAD Package
D Thermal Shutdown Protection
description
The TPS753xxQ and TPS751xxQ are low dropout regulators with integrated power-on reset and power-good (PG)
functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV
(TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is
disabled. TPS751xxQ and TPS753xxQ are designed to have fast transient response for larger load current
changes.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an
output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the
PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading
(typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when EN
is connected to a low level voltage. This LDO family also features a sleep mode;
applying a TTL high signal to EN
(enable) shuts down the regulator, reducing the quiescent current to less than 1
µA at T
J
= 25°C.
For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output, which can be used to
implement a power-on reset or a low-battery indicator.
Copyright 2008, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(TOP VIEW)
GND/HEATSINK
NC
IN
IN
EN
PG or RESET
FB/SENSE
OUTPUT
OUTPUT
GND/HEATSINK
GND/HEATSIN
K
NC
NC
GND
NC
NC
NC
NC
NC
GND/HEATSIN
K
NC − No internal connection
PG is on the TPS751xx and RESET
is on the TPS753xx
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SGLS159A − APRIL 2003 − REVISED APRIL 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The RESET (SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and
microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ
monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
When the output reaches 95% of its regulated voltage, RESET
goes to a high-impedance state after a 100-ms delay.
RESET
goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition)
of its regulated voltage.
The TPS751xxQ or TPS753xxQ is offered in 1.5-V, 1.8-V, 2.5-V and 3.3-V fixed-voltage versions and in an
adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a
maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available
in 20-pin TSSOP (PWP) packages.
T
J
− Junction Temperature − °C
−40 10 11060
− Dropout Voltage − mV
V
DO
TPS75x33Q
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
160
250
200
150
100
50
0
I
O
= 0.5 A
I
O
= 1.5 A
t − Time − ms
TPS75x15Q
LOAD TRANSIENT RESPONSE
I − Output Current − A
O
V
O
− Change in
Output Voltage − mV
−100
0
032145768910
0
50
−50
I
L
=1.5 A
C
L
=100 µF (Tantalum)
V
O
=1.5 V
−150
1.5
AVAILABLE OPTIONS
†‡
T
J
OUTPUT VOLTAGE
TSSOP (PWP)
T
J
OUTPUT VOLTAGE
(TYP)
PG RESET
3.3 V TPS75133QPWPRQ1
§
TPS75333QPWPRQ1
2.5 V TPS75125QPWPRQ1
§
TPS75325QPWPRQ1
−40°C to 125°C
1.8 V TPS75118QPWPRQ1
§
TPS75318QPWPRQ1
−40 C to 125 C
1.5 V TPS75115QPWPRQ1
§
TPS75315QPWPRQ1
Adjustable 1.5 V to 5 V TPS75101QPWPRQ1
§
TPS75301QPWPRQ1
NOTE: The TPS75x01 is programmable using an external resistor divider (see application
information). R suffix indicates tape and reel.
For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§
Product preview
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SGLS159A − APRIL 2003 − REVISED APRIL 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
See application information section for capacitor selection details.
PG or
RESET
OUT
OUT
4
3
5
IN
IN
EN
GND
17
6
8
9
V
I
0.22 µF
PG or RESET
Output
V
O
47 µF
+
C
O
SENSE
7
Figure 1. Typical Application Configuration (For Fixed Output Options)
functional block diagram—adjustable version
100 ms Delay
(for RESET
Option)
_
+
V
ref
= 1.1834 V
OUT
FB
EN
GND
PG or RESET
_
+
IN
External to the device
R1
R2
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