I
RMS
+ I
OUT
D
Ǹ
+ I
OUT
V
OUT
V
IN
Ǹ
P
DISS
+
ǒ
I
RMS
Ǔ
2
@ R
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Current Limit (Buck Controllers)
An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These
resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins
that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an
internal reference to determine if an over-current condition exists. When current limit is exceeded, the external
PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10ns any time the PMOS is
turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled.
Current limit is calculated using the V
IS1
or V
IS2
specification in the Electrical Characteristics section, shown in
Equation 1:
(1)
The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current
calculated by Equation 2:
(2)
For low-cost applications the I
S1,2
pin can be connected to the drain of the PMOS, using R
DS,ON
instead of R1 or
R2 to set current limit. Variations in the PMOS R
DS,ON
must be taken into account to ensure that current limit will
protect external components such as the inductor, the diode, and the switch itself from damage as a result of
over-current.
Short-Circuit Protection (Buck Controllers)
In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be
exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the
feedback pin is lower than the reference voltage. When the output is shorted (V
FB
is zero), minimum off-time is
increased to approximately 4ms. The increase in off-time is proportional to the difference between the voltage at
the feedback pin and the internal reference.
Soft-Start (Buck Controllers)
The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing
requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the
turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. Refer
to the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be
discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and
cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low,
any charge on the SS pin is discharged by an on-chip pull-down transistor. When EN1 is driven high, an on-chip
current source starts charging the external soft-start capacitor C
SS1
. The voltage on the capacitor is compared to
the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage
drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the
minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the
soft-start time over a wide range for most applications. For detailed information on choosing C
SS1
and C
SS2
, see
the section, Soft-Start Capacitor Selection (Buck Controllers) .
14 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
