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TPS75003RHLR

Part # TPS75003RHLR
Description TRIPLE-SUPPLY PWR MGMT IC
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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PRODUCT PREVIEW
FEATURES DESCRIPTION
APPLICATIONS
3A
BUCK1
3A
BUCK2
300mA
LDO
IN1
EN1
SS1
IS1
SW1
FB1
IN2
EN2
SS2
IS2
SW2
FB2
IN3
EN3
SS3
OUT3
FB3
DGND AGND
TPS75003
IN3
OUT3
FB1
FB2
20
1
11
10
DGND
SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
19
18
17
16
15
14
13
12
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
2
3
4
5
6
7
8
9
TPS75003
SBVS052A OCTOBER 2004 REVISED DECEMBER 2004
Triple-Supply Power Management IC
for Powering FPGAs and DSPs
Two Buck Controllers Providing up to 3A and
The TPS75003 is a complete power management
One 300mA LDO for Powering 3 Supplies
solution for FPGA, DSP and other multi-supply appli-
cations. The device has been tested with and meets
Tested and Endorsed by Xilinx for Powering
all of the Xilinx Spartan-3 and Spartan-3L start-up
the Spartan™-3 and Spartan-3L FPGAs
profile requirements, including monotonic voltage
Adjustable (1.2V to 6.5V for Bucks, 0.9V to
ramp and minimum voltage rail rise time. Independent
6.5V for LDO) Output Voltages on All
Enables for each output allow sequencing to minimize
Channels
demand on the power supply at start-up. Soft-start on
each supply limits inrush current during start-up. Two
Independent Soft-Start for Each Supply
integrated buck controllers allow efficient,
Independent Enable for Each Supply
cost-effective voltage conversion for both low and
LDO Stable with Small 2.2µF Ceramic Output
high current supplies such as core and I/O. A 300mA
Cap
LDO is integrated to provide an auxiliary rail such as
V
CCAUX
on the Xilinx Spartan-3 FPGA. All three
Input Voltage Range: 2.2V to 6.5V
supply voltages are offered in user-programmable
Small, Low-Profile 4.5mm x 3.5mm x 0.9mm
options for maximum flexibility.
QFN Package
The TPS75003 is fully specified from -40 ° C to +85 ° C
and is offered in a QFN package, yielding a highly
compact total solution size with high power dissi-
FPGA Supplies
pation capability.
DSP/ASIC Supplies
Split Supply Applications
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Spartan is a trademark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the forma-
Copyright © 2004, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
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PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS75003
SBVS052A OCTOBER 2004 REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
SPECIFIED
PACKAGE-LEAD ORDERING TRANSPORT
PRODUCT V
OUT
TEMPERATURE
DESIGNATOR NUMBER MEDIA, QUANTITY
RANGE, T
A
Buck1: Adjustable
TPS75003 Buck2: Adjustable 4.5x3.5 QFN-20 (RHL) -40 ° C to +85 ° C TPS75003RHLR Tape and Reel, 3000
LDO: Adjustable
over operating free-air temperature range (unless otherwise noted)
(1)
TPS75003 UNIT
V
INX
range (IN1, IN2, IN3) -0.3 to +7.0 V
V
ENX
range (EN1, EN2, EN3) -0.3 to V
INX
+0.3 V
V
SWX
range (SW1, SW2, SW3) -0.3 to V
INX
+0.3 V
V
ISX
range (IS1, IS2, IS3) -0.3 to V
INX
+0.3 V
V
OUT3
range -0.3 to +7.0 V
V
SSX
range (SS1, SS2, SS3) -0.3 to V
INX
+0.3 V
V
FBX
range (FB1, FB2, FB3) -0.3 to +3.3 V
Peak LDO output current (I
OUT3
) Internally limited
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
J
-55 to +150 ° C
Storage temperature range -65 to +150 ° C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DERATING FACTOR T
A
25 ° C T
A
= 70 ° C T
A
= 85 ° C
BOARD R
Θ JC
R
Θ JA
ABOVE T
A
= 25 ° C POWER RATING POWER RATING POWER RATING
Reference
Layout
(1)
(1) Refer to PCB Layout section. Internal power dissipation limits are determined by LDO operation: P
DISS
= (V
IN3
V
OUT3
) x I
OUT3
.
2
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PRODUCT PREVIEW
ELECTRICAL CHARACTERISTICS
TPS75003
SBVS052A OCTOBER 2004 REVISED DECEMBER 2004
V
EN1
= V
IN1
, V
EN2
= V
IN2
, V
EN3
= V
IN3
, V
IN1
= V
IN2
= V
IN3
= 3.0V, V
OUT1
= V
OUT2
= V
OUT3
= 2.5V, C
OUT1
= C
OUT2
= 47µF,
C
OUT3
= 2.2µF, T
A
= -40 ° C to +85 ° C, unless otherwise noted. Typical values are at T
A
= 25 ° C.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Supply and Logic
Input Voltage Range (IN1, IN2,
V
INX
2.2 6.5 V
IN3)
(1)
Quiescent Current, I
Q
= I
DGND
+
I
Q
I
OUT1
= I
OUT2
= 0mA, I
OUT3
= 1mA 100 150 µA
I
AGND
I
SHDN
Shutdown Supply Current V
EN1
= V
EN2
= V
EN3
= 0V 0.3 3.0 µA
Enable High, enabled
V
IHX
1.3 V
INX
V
(EN1, EN2, EN3)
Enable Low, shutdown
V
ILX
0 0.3 V
(EN1, EN2, EN3)
I
ENX
Enable pin current (EN1, EN2, EN3) 0.01 0.5 µA
Buck Controllers 1 and 2
V
OUT1,2
Adjustable Output Voltage Range
(2)
V
FBX
V
INX
V
V
FB1,2
Feedback Voltage (FB1, FB2) 1.2 V
Feedback Voltage Accuracy
(1)
2.8V V
IN1,2
6.5V -4 +4 %
(FB1, FB2)
I
FB1,2
Current into FB1, FB2 pins 0.01 0.5 µA
Reference Voltage for Current
V
IS1,2
90 105 120 mV
Sense
I
IS1,2
Current into IS1, IS2 Pins 0.01 0.5 µA
Measured with the circuit in Fig-
V
OUT%
/ V
IN
Line Regulation
(1)
ure 1 , 0.6 % / V
V
OUT
+ 0.5V V
IN
6.5V
Measured with the circuit in Fig-
V
OUT%
/ I
OUT
Load Regulation ure 1 , 0.6 % / A
1mA I
OUT
2A
Measured with the circuit in Fig-
n
1,2
Efficiency
(3)
94 %
ure 1 , I
OUT
= 1A
Measured with the circuit in Fig-
ure 1 ,
t
STR1,2
Startup Time
(3)
5 ms
R
L
= 6 , C
OUT
= 100µF, C
SS
=
2.2nF
V
IN1,2
> 2.5V 4
Gate Driver P-Channel MOSFET
R
DS,ON1,2
On-Resistance
V
IN1,2
= 2.2V 6
V
IN1,2
> 2.5V 4
Gate Driver N-Channel MOSFET
R
DS,ON1,2
On-Resistance
V
IN1,2
= 2.2V 6
I
SW1,2
Minimum Gate Drive Current TBD mA
t
ON
Minimum On Time 1.36 1.6 1.84 µs
t
OFF
Minimum Off Time 0.44 0.55 0.86 µs
LDO
V
OUT3
Output Voltage Range 1.0 6.5 - V
DO
V
V
FB3
Feedback Pin Voltage 0.507 V
2.85V V
IN3
6.5V
Feedback Pin Voltage Accuracy
(1)
-4.0 +4.0 %
1mA I
OUT3
300mA
V
OUT%
/ V
IN
Line Regulation
(1)
V
OUT3
+ 0.5V V
IN3
6.5V 0.75 % / V
V
OUT%
/ I
OUT
Load Regulation 10mA I
OUT3
300mA 0.01 % / mA
(1) To be in regulation, minimum V
IN1
(or V
IN2
) must be greater than V
OUT1,NOM
(or V
OUT2,NOM
) by an amount determined by external
components. Minimum V
IN3
= V
OUT3
+ V
DO
or 2.2V, whichever is greater.
(2) Maximum V
OUT
is dependent on external components and will be less than V
IN
.
(3) Depends on external components.
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