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MSP430F233TPM

Part # MSP430F233TPM
Description MCU 16-bit MSP430 RISC 8KB Flash 2.5V/3.3V 64-Pin LQFP Tra
Category IC
Availability In Stock
Qty 218
Qty Price
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184 + $1.77794
Manufacturer Available Qty
Texas Instruments
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Texas Instruments
  • Shipping Freelance Stock: 112
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt flag register 1 and 2
rw-1 rw-(0)
Address
0x2h
01234567
OFIFG WDTIFG
rw-0
NMIIFG
rw-(1)
PORIFG
rw-(0)
RSTIFG
Interrupt Flag register 1
WDTIFG Set on watchdog-timer overflow or security key violation.
Reset on V
CC
power-on, or a reset condition at the RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
PORIFG Power-on interrupt flag. Set on V
CC
power-up.
RSTIFG External reset interrupt flag. Set on a reset condition at RST
/NMI pin in reset mode. Reset
on V
CC
power--up.
NMIIFG Set via RST
/NMI pin
Address
0x3h
01234567
rw-0
UCA0RXIFG
rw-1
UCA0TXIFG
rw-0
UCB0RXIFG
rw-1
UCB0TXIFG
Interrupt Flag register 2
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
Legend rw: Bit can be read and written.
rw-0,1: Bit can be read and written. It is Reset or Set by PUC.
rw-(0,1) Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
20
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
memory organization (MSP430F23x, MSP430F24x(1), MSP430F2410)
MSP430F233 MSP430F235
MSP430F249
MSP430F2491
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB
0xFFFF to 0xFFC0
0xFFFF to 0xE000
16KB
0xFFFF to 0xFFC0
0xFFFF to 0xC000
60KB
0xFFFF to 0xFFC0
0xFFFF to 0x1100
RAM (total) Size 1KB
0x05FF to 0x0200
2KB
0x09FF to 0x0200
2KB
0x09FF to 0x0200
Information memory Size
Flash
256 Byte
0x10FF to 0x1000
256 Byte
0x10FF to 0x1000
256 Byte
0x10FF to 0x1000
Boot memory Size
ROM
1KB
0x0FFF to 0x0C00
1KB
0x0FFF to 0x0C00
1KB
0x0FFF to 0x0C00
RAM Size 1KB
0x05FF to 0x0200
2KB
0x09FF to 0x0200
2KB
0x09FF to 0x0200
Peripherals 16-bit
8-bit
SFR
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
MSP430F247
MSP430F2471
MSP430F248
MSP430F2481
MSP430F2410
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0xFFFF to 0xFFC0
0xFFFF to 0x8000
48KB
0xFFFF to 0xFFC0
0xFFFF to 0x4000
56KB
0xFFFF to 0xFFC0
0xFFFF to 0x2100
RAM (Total)
Extended
Mirrored
Size
Size
Size
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
4KB
0x20FF to 0x1100
2KB
0x20FF to 0x1900
2KB
0x18FF to 0x1100
Information memory Size
Flash
256 Byte
0x10FF to 0x1000
256 Byte
0x10FF to 0x1000
256 Byte
0x10FF to 0x1000
Boot memory Size
ROM
1KB
0x0FFF to 0x0C00
1KB
0x0FFF to 0x0C00
1KB
0x0FFF to 0x0C00
RAM (mirrored at
0x18FF to 0x01100)
Size 2KB
0x09FF to 0x0200
2KB
0x09FF to 0x0200
2KB
0x09FF to 0x0200
Peripherals 16-bit
8-bit
SFR
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader
(literature number SLAA089).
BSL FUNCTION PM, RTD PACKAGE PINS
Data Transmit 13 - P1.1
Data Receive 22 - P2.2
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
21
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
flash memory
The flash memory can be programmed via the JTAG port, the BSL, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0--n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
D Flash content integrity check with marginal read modes.
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
oscillator and system clock
The clock system in the MSP430x23x, MSP43x24x(1), and MSP430F2410 family of devices is supported by
the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power,
low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator.
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or a very low
power LF oscillator
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
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