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MSP430F2101TDWR

Part # MSP430F2101TDWR
Description IC MCU 16BIT 1KB FLASH 20SOIC
Category IC
Availability In Stock
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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  
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption
− Active Mode: 250 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
D Ultrafast Wake-Up From Standby Mode in
less than 1 µs
D 16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
D Basic Clock Module Configurations:
− Internal Frequencies up to 16MHz with
4 calibrated Frequencies to ±1%
− 32-kHz Crystal
− High-Frequency Crystal up to 16MHz
− Resonator
− External Digital Clock Source
D 16-Bit Timer_A With Three
Capture/Compare Registers
D On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D Brownout Detector
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
D Bootstrap Loader
D On Chip Emulation Module
D Family Members Include:
MSP430F2101: 1KB + 256B Flash Memory
128B RAM
MSP430F2111: 2KB + 256B Flash Memory
128B RAM
MSP430F2121: 4KB + 256B Flash Memory
256B RAM
MSP430F2131: 8KB + 256B Flash Memory
256B RAM
D Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin Plastic
Small-Outline Thin (TSSOP) Package,
20-Pin TVSOP and 24-Pin QFN
D For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.
The MSP430x21x1 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile
analog comparator and sixteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application. The analog comparator provides slope A/D conversion capability.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
PLASTIC
20-PIN TVSOP
(DGV)
PLASTIC
24-PIN QFN
(RGE)
−40°C to 85°C
MSP430F2101IDW
MSP430F2111IDW
MSP430F2101IPW
MSP430F2111IPW
MSP430F2101IDGV
MSP430F2111IDGV
MSP430F2101IRGE
MSP430F2111IRGE
−40°C to 85°C
MSP430F2111IDW
MSP430F2121IDW
MSP430F2131IDW
MSP430F2111IPW
MSP430F2121IPW
MSP430F2131IPW
MSP430F2111IDGV
MSP430F2121IDGV
MSP430F2131IDGV
MSP430F2111IRGE
MSP430F2121IRGE
MSP430F2131IRGE
−40°C to 105°C
MSP430F2101TDW
MSP430F2111TDW
MSP430F2121TDW
MSP430F2131TDW
MSP430F2101TPW
MSP430F2111TPW
MSP430F2121TPW
MSP430F2131TPW
MSP430F2101TDGV
MSP430F2111TDGV
MSP430F2121TDGV
MSP430F2131TDGV
MSP430F2101TRGE
MSP430F2111TRGE
MSP430F2121TRGE
MSP430F2131TRGE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004 − 2006 Texas Instruments Incorporated
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
device pinout
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to V
SS
recommended
10
1
9
7
8
6
5
4
3
2
11
20
12
14
13
15
16
17
18
19
TEST
V
CC
P2.5/CA5
V
SS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST
/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
P2.3/TA1/CA0
P1.4/SMCLK/TCK
1
6
5
4
3
2
18
13
14
15
16
17
712111098
1924 23 22 21 20
TEST
V
CC
P2.5/CA5
V
SS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
P2.3/TA1/CA0
P1.4/SMCLK/TCK
NC
NC
NC
NC
functional block diagram
Basic Clock
System+
RAM
256B
256B
128B
128B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
8kB
4kB
2kB
1kB
ACLK
XIN
Port P1
8I/O
Interrupt
capability,
pull−up/down
resistors
Comparator
_A+
8 Channel
Input Mux
P1.x & JTAG
8
P2.x &
XIN/XOUT
8
Port P2
8 I/O
Interrupt
capability,
pull−up/down
resistors
MDB
MAB
NOTE: See port schematics section for detailed I/O information.

  
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
DW, PW, or DGV RGE
I/O
DESCRIPTION
NAME
NO. NO.
I/O
DESCRIPTION
P1.0/TACLK 13 13 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
P1.1/TA0 14 14 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1 15 15 I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 16 16 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK 17 17 I/O General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/TMS 18 18 I/O General-purpose digital I/O pin / Timer_A, compare: Out0 output
Test Mode Select input for device programming and test
P1.6/TA1/TDI/TCLK 19 20 I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output
Test Data Input or Test Clock Input for programming and test
P1.7/TA2/TDO/TDI
20 21 I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output
Test Data Output or Test Data Input for programming and test
P2.0/ACLK/CA2 8 6 I/O General-purpose digital I/O pin / ACLK output
Comparator_A+, CA2 input
P2.1/INCLK/CA3 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK
Comparator_A+, CA3 input
P2.2/CAOUT/
TA0/CA4
10 8 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive
Comparator_A+, output / CA4 input
P2.3/CA0/TA1 11 10 I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output
Comparator_A+, CA0 input
P2.4/CA1/TA2 12 11 I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output
Comparator_A+, CA1 input
P2.5/CA5 3 24 I/O General-purpose digital I/O pin
Comparator_A+, CA5 input
XIN/P2.6/CA6 6 4 I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
Comparator_A+, CA6 input
XOUT/P2.7/CA7 5 3 I/O Output terminal of crystal oscillator
general-purpose digital I/O pin
Comparator_A+, CA7 input
RST/NMI 7 5 I Reset or nonmaskable interrupt input
TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse
is connected to TEST.
V
CC
2 23 Supply voltage
V
SS
4 2 Ground reference
QFN Pad NA Package Pad NA QFN package pad connection to V
SS
recommended.
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
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