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MSP430F233TPM

Part # MSP430F233TPM
Description MCU 16-bit MSP430 RISC 8KB Flash 2.5V/3.3V 64-Pin LQFP Tra
Category IC
Availability In Stock
Qty 218
Qty Price
1 - 45 $2.86205
46 - 91 $2.27663
92 - 137 $2.14654
138 - 183 $1.99476
184 + $1.77794
Manufacturer Available Qty
Texas Instruments
  • Shipping Freelance Stock: 106
    Ships Immediately
Texas Instruments
  • Shipping Freelance Stock: 112
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions -- MSP430F24x1
TERMINAL
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME NO.
I
/
O DESCRIPTION
AV
CC
64 Analog supply voltage, positive. Supplies only the analog portion of ADC12.
AV
SS
62 Analog supply voltage, negative. Supplies only the analog portion of ADC12.
DV
CC
1 Digital supply voltage, positive. Supplies all digital parts.
DV
SS
63 Digital supply voltage, negative. Supplies all digital parts.
P1.0/TACLK/
CAOUT
12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / Comparator_A output
P1.1/TACLK 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output / BSL transmit
P1.2/TA0 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA1 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output
P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input
P2.1/TAINCLK/
CA3
21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
/CA4
22 I/O
General-purpose digital I/O / Timer_A, capture: CCI0B input / Comparator_A output/BSL
receive/Comparator_A input
P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output / Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output / Comparator_A input
P2.5/Rosc/CA5 25 I/O
General-purpose digital I/O / i nput for external resistor defining the DCO nominal frequency / Comparator_A
input
P2.6/
ADC12CLK
/CA6
26 I/O General-purpose digital I/O / conversion clock 12-bit ADC / Comparator_A input
P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input
P3.0/UCB0STE/
UCA0CLK
28 I/O General-purpose digital I/O / USCI B0 slave transmit enable/USCI A0 clock input/output
P3.1/UCB0SIMO/
UCB0SDA
29 I/O General-purpose digital I/O / USCI B0 slave in/master out in SPI mode, SDA I
2
CdatainI
2
C mode
P3.2/UCB0SOMI/
UCB0SCL
30 I/O General-purpose digital I/O / USCI B0 slave out/master in in SPI mode, SCL I
2
C clock in I
2
C mode
P3.3/UCB0CLK/
UCA0STE
31 I/O General-purpose digital I/O / USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/UCA0TXD/
UCA0SIMO
32 I/O
General-purpose digital I/O / USCIA transmit data output in UART mode, slave data in/master out in SPI
mode
P3.5/UCA0RXD/
UCA0SOMI
33 I/O
General-purpose digital I/O / USCI A0 receive data input in UART mode, slave data out/master in in SPI
mode
P3.6/UCA1TXD/
UCA1SIMO
34 I/O
General-purpose digital I/O / USCI A1 transmit data output in UART mode, slave data in/master out in SPI
mode
P3.7/UCA1RXD/
UCA1SOMI
35 I/O
General-purpose digital I/O / USCIA1 receive data input in UART mode, slave data out/master in in SPI
mode
P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions -- MSP430F24x1 (Continued)
TERMINAL
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME NO.
I
/
O DESCRIPTION
P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3 39 I/O General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4 40 I/O General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5 41 I/O General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6 42 I/O General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input
P5.0/UCB1STE/
UCA1CLK
44 I/O General-purpose digital I/O / USCI B1 slave transmit enable/USCI A1 clock input/output
P5.1/UCB1SIMO/
UCB1SDA
45 I/O General-purpose digital I/O / USCI B1 slave in/master out in SPI mode, SDA I
2
CdatainI
2
C mode
P5.2/UCB1SOMI/
UCB1SCL
46 I/O General-purpose digital I/O / USCI B1 slave out/master in in SPI mode, SCL I
2
C clock in I
2
C mode
P5.3/UCB1CLK/
UCA1STE
47 I/O General-purpose digital I/O / USCI B1 clock input/output, USCI A1 slave transmit enable
P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock M CLK output
P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output
P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT
51 I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance -- Timer_B TB0 to
TB6/SVS comparator output
P6.0 59 I/O General-purpose digital I/O
P6.1 60 I/O General-purpose digital I/O
P6.2 61 I/O General-purpose digital I/O
P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O General-purpose digital I/O / SVS input
XT2OUT 52 O Output terminal of crystal oscillator XT2
XT2IN 53 I Input port for crystal oscillator XT2
RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
DV
SS
10 I Connected to DV
SS
Reserved 7 O Reserved, do not connect externally
DV
SS
11 I Connected to DV
SS
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output port for crystal oscillator XT1. Standard or watch crystals c an be connected.
QFN Pad NA NA QFN package pad connection to DV
SS
recommended (RTD package only)
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, s tack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set c onsists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on w ord and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register D
D
MOV Rs,Rd MOV R10,R11 R10 ----> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)----> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) ----> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) ----> M(TCDAT)
Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6)
Indirect
autoincrement
D MOV @Rn+,Rm MOV @R10+,R11
M(R10) ----> R11
R10 + 2----> R10
Immediate D MOV #X,TONI MOV #45,TONI #45 ----> M(TONI)
NOTE: S = source, D = destination
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