MAX3100

SPI/Microwire-Compatible

UART in QSOP-16

_______________________________________________________________________________________ 7

The receiver section receives data in serial form. The

MAX3100 detects a start bit on a high-to-low RX transi-

tion (Figure 3). An internal clock samples data at 16

times the data rate. The start bit can occur as much as

one clock cycle before it is detected, as indicated by

the shaded portion. The state of the start bit is defined

as the majority of the 7th, 8th, and 9th sample of the

internal 16x baud clock. Subsequent bits are also

majority sampled. Receive data is stored in an 8-word

FIFO. The FIFO is cleared if it overflows.

The on-board oscillator can use a 1.8432MHz or

3.6864MHz crystal, or it can be driven at X1 with a 45%

to 55% duty-cycle square wave.

SPI Interface

The bit streams for DIN and DOUT consist of 16 bits,

with bits assigned as shown in the

MAX3100

Operations

section. DOUT transitions on SCLK’s falling

edge, and DIN is latched on SCLK’s rising edge (Figure

4). Most operations, such as the clearing of internal

registers, are executed only on CS’s rising edge. The

DIN stream is monitored for its first two bits to tell the

UART the type of data transfer being executed (Write

Config, Read Config, Write Data, Read Data).

Only 16-bit words are expected. If CS goes high in the

middle of a transmission (any time before the 16th bit),

the sequence is aborted (i.e., data does not get written

to individual registers). Every time CS goes low, a new

16-bit stream is expected. An example of a write con-

figuration is shown in Figure 4.

BAUD

BLOCK

2 3 4 5 6 7 8 9

ONE BAUD PERIOD

10 11

MAJORITY

CENTER

SAMPLER

12 13 14 15 16

Figure 3. Start-Bit Timing

SCLK

DIN

DOUT

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DATA

UPDATED

11 FEN SHDN TM RM PM RAM IR ST PE L B3 B2 B1 B0

R T 00 0 0 0 0 0 0 0 0 0 0 0 0

Figure 4. SPI Interface (Write Configuration)

MAX3100

SPI/Microwire-Compatible

UART in QSOP-16

8 _______________________________________________________________________________________

MAX3100 Operations

Write Operations

Table 1 shows write-configuration data. A 16-bit

SPI/Microwire write configuration clears the receive

FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt

registers. RTS and CTS remain unchanged. The new

configuration is valid on CS’s rising edge if the transmit

buffer is empty (T = 1) and transmission is over. If the

latest transmission has not been completed, the regis-

ters are updated when the transmission is over (T = 0).

The write-configuration bits (FEN, SHDNi, IR, ST, PE, L,

B3–B0) take effect after the current transmission is

over. The mask bits (TM, RM, PM, RAM) take effect

immediately after the 16th clock’s rising edge at SCLK.

Read Operations

Table 2 shows read-configuration data. This register

reads back the last configuration written to the

MAX3100. The device enters test mode if bit 0 = 1. In

this mode, if CS = 0, the RTS pin acts as the 16x clock

generator’s output. This may be useful for direct baud-

rate generation (in this mode, TX and RX are in digital

loopback).

Normally, the write-data register loads the TX-buffer

data, set the TE bit. Setting the TE bit high inhibits the

write command (Table 3).

Reading data clears the R bit and interrupt IRQ (Table 4).

Table 5 shows read/write operation and power-on reset

state (POR), and describes each bit used in program-

ming the MAX3100. Figure 5 shows parity and word-

length control.

D6t

D6r

D7t

D7r

15 2

DIN 1 D2t

DOUT R D2r

BIT 3

D3t

D3r

D0t

D0r

D1t

D1r

D4t

D4r

D5t

D5r

RA/FE

RTS

CTS

D6r

D7r

15 2

DIN 0 0

DOUT R D2r

BIT 3

D3r

D0r

D1r

D4r

D5r

RA/FE

CTS

Table 3. Write Data (D15, D14 = 1, 0)

Table 4. Read Data (D15, D14 = 0, 0)

15 2

DIN 0 0

DOUT R B2

BIT 3

TEST

RAM

SHDNo

FEN

Table 2. Read Configuration (D15, D14 = 0, 1)

RAM

SHDNi

FEN

15 14

DIN 1

DOUT R

BIT

Table 1. Write Configuration (D15, D14 = 1, 1)

MAX3100

SPI/Microwire-Compatible

UART in QSOP-16

_______________________________________________________________________________________ 9

POR

STATE

DESCRIPTION

0000

XPr r

Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit

transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive

data (see the

Nine-Bit Networks

section).

IR r Reads the value of the IR bit.

READ/

WRITE

B0–B3 w Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).

B0–B3 r Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.

BIT

NAME

Bit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words

(9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1).

L r Reads the value of the L bit.

Pt w

Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be

useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is

ignored in transmit mode (see the

Nine-Bit Networks

section).

00000000

D0r–D7r r

Eight data bits read from the receive FIFO or the receive register. These will be all 0s when

the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0.

FEN

FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled.

FEN

FIFO-Enable Readback. FEN’s state is read.

IR w Enables the IrDA timing mode when IR = 1.

change

CTS r

Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic

high).

D0t–D7t w

Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored

when L = 1.

Table 5. Bit Descriptions

0PE w

Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt

bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to

be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not

calculate parity.

0PE r Reads the value of the Parity-Enable bit.

Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 6).

Reads the value of the PM bit (Table 6).

0R r

Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the

receive register or FIFO.

Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 6).

Reads the value of the RM bit (Table 6).

RAM

Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 6).

RAM

Reads the value of the RAM bit (Table 6).

0RTS w

Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS

bit = 0 sets the RTS pin = logic high).

Part #	MAX3100CEE
Description	SPI/MICROWIRE-COMPATIBLE UARTIN A QSOP-16 P - Bulk
Category	IC
Availability	In Stock
Qty	175

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MAX3100CEE

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