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LP2997MR

Part # LP2997MR
Description IC DDR-II TERM REG 8SOPWRPAD
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

V
TT
LP2997
PV
IN
V
DDQ
V
REF
AV
IN
V
REF
=
0.9V
V
SENSE
GND
+
+
+
AV
IN
= 2.5V
V
TT
= 0.9V
SD
SD
V
DDQ
= 1.8V
C
IN
C
OUT
C
REF
LP2997
www.ti.com
SNVS295F MAY 2004REVISED APRIL 2013
LP2997 DDR-II Termination Regulator
Check for Samples: LP2997
1
FEATURES
DESCRIPTION
The LP2997 linear regulator is designed to meet the
2
Source and Sink Current
JEDEC SSTL-18 specifications for termination of
Low Output Voltage Offset
DDR-II memory. The device contains a high-speed
No External Resistors Required
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
Linear Topology
through while delivering 500mA continuous current
Suspend to Ram (STR) Functionality
and transient peaks up to 900mA in the application as
Low External Component Count
required for DDR-II SDRAM termination. The LP2997
also incorporates a V
SENSE
pin to provide superior
Thermal Shutdown
load regulation and a V
REF
output as a reference for
Available in SOIC-8, SO PowerPAD-8 Packages
the chipset and DIMMs.
An additional feature found on the LP2997 is an
APPLICATIONS
active low shutdown (SD) pin that provides Suspend
DDR-II Termination Voltage
To RAM (STR) functionality. When SD is pulled low
SSTL-18 Termination
the V
TT
output will tri-state providing a high
impedance output, but, V
REF
will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
Typical Application Circuit
Figure 1. Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VDDQ
PVIN
AVIN
1
2
3
4
8
7
6
5
VSENSE
VREF
SD
GND
VTT
GND
VDDQ
PVIN
AVIN
1
2
3
4
8
7
6
5
VSENSE
VREF
SD
GND
VTT
LP2997
SNVS295F MAY 2004REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 2. SO PowerPAD-8 Layout Figure 3. SOIC-8 Layout
See Package Number DDA (R-PDSO-G8) See Package Number D0008A
PIN DESCRIPTIONS
SOIC-8 Pin or
Name Function
SO PowerPAD-8 Pin
1 GND Ground
2 SD Shutdown
3 VSENSE Feedback pin for regulating V
TT
.
4 VREF Buffered internal reference voltage of V
DDQ
/2
5 VDDQ Input for internal reference equal to V
DDQ
/2
6 AVIN Analog input pin
7 PVIN Power input pin
8 VTT Output voltage for connection to termination resistors
EP Exposed pad thermal connection Connect to Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
AVIN to GND 0.3V to +6V
PVIN to GND -0.3V to AVIN
VDDQ
(3)
0.3V to +6V
Storage Temp. Range 65°C to +150°C
Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 260°C
SOIC-8 Thermal Resistance (θ
JA
) 151°C/W
SO PowerPAD-8 Thermal Resistance (θ
JA
) 43°C/W
Minimum ESD Rating
(4)
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions
see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin.
Operating Range
Junction Temp. Range
(1)
0°C to +125°C
AVIN to GND 2.2V to 5.5V
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θ
JA
= 151.2° C/W junction to ambient with no heat sink.
2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LP2997
LP2997
www.ti.com
SNVS295F MAY 2004REVISED APRIL 2013
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25°C and limits in boldface type apply over the full Operating
Temperature Range (T
J
= 0°C to +125°C)
(1)
. Unless otherwise specified, AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.
Symbol Parameter Conditions Min Typ Max Units
V
REF
V
REF
Voltage PVIN = VDDQ = 1.7V 0.837 0.860 0.887
PVIN = VDDQ = 1.8V 0.887 0.910 0.937 V
PVIN = VDDQ = 1.9V 0.936 0.959 0.986
Z
VREF
V
REF
Output Impedance I
REF
= -30 to +30 μA 2.5 k
V
TT
V
TT
Output Voltage I
OUT
= 0A
PVIN = VDDQ = 1.7V 0.822 0.856 0.887
PVIN = VDDQ = 1.8V 0.874 0.908 0.939
PVIN = VDDQ = 1.9V 0.923 0.957 0.988
V
I
OUT
= ±0.5A
(2)
PVIN = VDDQ = 1.7V 0.828 0.856 0.890
PVIN = VDDQ = 1.8V 0.878 0.908 0.940
PVIN = VDDQ = 1.9V 0.928 0.957 0.990
Vos
TT
/V
TT
V
TT
Output Voltage Offset I
OUT
= 0A -25 0 25
(V
REF
-V
TT
) I
OUT
= -0.5A -25 0 25 mV
I
OUT
= +0.5A -25 0 25
I
Q
Quiescent Current
(3)
I
OUT
= 0A
(3)
320 500 µA
Z
VDDQ
VDDQ Input Impedance 100 k
I
SD
Quiescent Current in SD = 0V 115 150 µA
Shutdown
(3)
I
Q_SD
Shutdown Leakage Current SD = 0V 2 5 µA
V
IH
Minimum Shutdown High 1.9 V
Level
V
IL
Maximum Shutdown Low 0.8 V
Level
I
SENSE
V
SENSE
Input Current 13 nA
T
SD
Thermal Shutdown See
(4)
165 Celsius
T
SD
_HYS Thermal Shutdown 10 Celsius
Hysteresis
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) V
TT
load regulation is tested by using a 10 ms current pulse and measuring V
TT
.
(3) Quiescent current defined as the current flow into AVIN.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, T
J(MAX)
, the junction to ambient thermal
resistance, θ
JA
, and the ambient temperature, T
A
. Exceeding the maximum allowable power dissipation will cause excessive die
temperature and the regulator will go into thermal shutdown.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
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