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LP2996LQ

Part # LP2996LQ
Description IC DDR TERMINATION REG 16LLP
Category IC
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National Semiconductor Corp
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

LP2996
June 29, 2012
DDR Termination Regulator
General Description
The LP2996 linear regulator is designed to meet the JEDEC
SSTL-2 specifications for termination of DDR-SDRAM. The
device contains a high-speed operational amplifier to provide
excellent response to load transients. The output stage pre-
vents shoot through while delivering 1.5A continuous current
and transient peaks up to 3A in the application as required for
DDR-SDRAM termination. The LP2996 also incorporates a
V
SENSE
pin to provide superior load regulation and a V
REF
output as a reference for the chipset and DIMMs.
An additional feature found on the LP2996 is an active low
shutdown (SD
) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low the V
TT
output will tri-
state providing a high impedance output, but, V
REF
will remain
active. A power savings advantage can be obtained in this
mode through lower quiescent current.
Features
Source and sink current
Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in SO-8, PSOP-8 or LLP-16 packages
Applications
DDR-I and DDR-II Termination Voltage
SSTL-2 and SSTL-3 Termination
HSTL Termination
Typical Application Circuit
20057518
© 2012 Texas Instruments Incorporated 200575 SNOSA40I www.ti.com
LP2996 DDR Termination Regulator
Connection Diagrams
Top View
20057502
LLP-16 Layout
20057503
PSOP-8 Layout
20057504
SO-8 Layout
Pin Descriptions
SO-8 Pin or
PSOP-8 Pin
LLP Pin Name Function
1 2 GND Ground
2 4 SD Shutdown
3 5 VSENSE Feedback pin for regulating V
TT
.
4 7 VREF Buffered internal reference voltage of V
DDQ
/2
5 8 VDDQ Input for internal reference equal to V
DDQ
/2
6 10 AVIN Analog input pin
7 11, 12 PVIN Power input pin
8 14, 15 VTT Output voltage for connection to termination resistors
- 1, 3, 6, 9, 13, 16 NC No internal connection
EP EP Exposed pad thermal connection. Connect to Ground.
Ordering Information
Order Number Package Type NSC Package Drawing Supplied As
LP2996M SO-8 M08A 95 Units per Rail
LP2996MX SO-8 M08A 2500 Units Tape and Reel
LP2996MR PSOP-8 MRA08A 95 Units per Rail
LP2996MRX PSOP-8 MRA08A 2500 Units Tape and Reel
LP2996LQ LLP-16 LQA16A 1000 Units Tape and Reel
LP2996LQX LLP-16 LQA16A 4500 Units Tape and Reel
www.ti.com 2
LP2996
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
AVIN to GND −0.3V to +6V
PVIN to GND -0.3V to AVIN
VDDQ (Note 2) −0.3V to +6V
Storage Temp. Range −65°C to +150°C
Junction Temperature 150°C
SO-8 Thermal Resistance (θ
JA
)
151°C/W
PSOP-8 Thermal Resistance (θ
JA
)
43°C/W
LLP-16 Thermal Resistance (θ
JA
)
51°C/W
Lead Temperature (Soldering, 10 sec) 260°C
ESD Rating (Note 3) 1kV
Operating Range
Junction Temp. Range (Note 4) 0°C to +125°C
AVIN to GND 2.2V to 5.5V
PVIN Supply Voltage 0 to AVIN
SD Input Voltage 0 to AVIN
Electrical Characteristics Specifications with standard typeface are for T
J
= 25°C and limits in boldface type
apply over the full Operating Temperature Range (T
J
= 0°C to +125°C) (Note 5). Unless otherwise specified,
AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6).
Symbol Parameter Conditions Min Typ Max Units
V
REF
V
REF
Voltage VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
1.135
1.235
1.335
1.158
1.258
1.358
1.185
1.285
1.385
V
Z
VREF
V
REF
Output Impedance
I
REF
= -30 to +30 μA
2.5
k
V
TT
V
TT
Output Voltage I
OUT
= 0A
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
1.125
1.225
1.325
1.159
1.259
1.359
1.190
1.290
1.390
V
I
OUT
= ±1.5A (Note 9)
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
1.125
1.225
1.325
1.159
1.259
1.359
1.190
1.290
1.390
Vos
TT
/V
TT
V
TT
Output Voltage Offset
(V
REF
-V
TT
)
I
OUT
= 0A
I
OUT
= -1.5A (Note 9)
I
OUT
= +1.5A (Note 9)
-20
-25
-25
0
0
0
20
25
25
mV
I
Q
Quiscent Current (Note 7) I
OUT
= 0A (Note 5) 320 500
µA
Z
VDDQ
VDDQ Input Impedance 100
k
I
SD
Quiescent Current in
Shutdown (Note 7)
SD = 0V 115 150 µA
I
Q_SD
Shutdown Leakage Current SD = 0V 2 5 µA
V
IH
Minimum Shutdown High
Level
1.9 V
V
IL
Maximum Shutdown Low
Level
0.8 V
I
V
V
TT
Leakage Current in
Shutdown
SD = 0V
V
TT
= 1.25V
1 10 µA
I
SENSE
V
SENSE
Input Current 13 nA
T
SD
Thermal Shutdown (Note 8) 165 Celcius
T
SD
_HYS Thermal Shutdown
Hysteresis
10 Celcius
3 www.ti.com
LP2996
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