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CAT24WC256K

Part # CAT24WC256K
Description EEPROM Serial-I2C 256K-bit 32K x 8 3.3V/5V 8-Pin SOIC EIAJ
Category IC
Availability In Stock
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Manufacturer Available Qty
CSI
Date Code: 0407
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1031, Rev. F
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
A1
NC
V
SS
A1
NC
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
V
SS
A0
PIN FUNCTIONS
Pin Name Function
A0, A1 Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
NC No Connect
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS EEPROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24WC256
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
Write protect feature
– entire array protected when WP at V
IH
100,000 program/erase cycles
100 year data retention
8-pin DIP or 8-pin SOIC
"Green" package options available
features a 64-byte page write buffer. The device oper-
ates via the I
2
C bus serial interface and is available in 8-
pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
CAT24WC256
256K-Bit I
2
C Serial CMOS EEPROM
1MHz I
2
C bus compatible*
1.8 to 6 volt operation
Low power CMOS technology
64-byte page write buffer
Self-timed write cycle with auto-clear
Commercial, industrial and automotive
temperature ranges
FEATURES
DIP Package (P, L)
SOIC Package (J, W, K, X)
D
OUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
EEPROM
512X512
V
CC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
V
SS
WP
SCL
SDA
512
512
A0
A1
(CAT24WC256 not recommended for new designs. See CAT24FC256 data sheet.)
CAT24WC256
2
Doc. No. 1031, Rev. F
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Symbol Parameter Test Conditions Min Typ Max Units
I
CC1
Power Supply Current - Read f
SCL
= 100 KHz 1 mA
V
CC
=5V
I
CC2
Power Supply Current - Write f
SCL
= 100KHz 3 mA
V
CC
=5V
I
SB
(5)
Standby Current V
IN
= GND or V
CC
1 µA
V
CC
=5V
I
LI
Input Leakage Current V
IN
= GND to V
CC
1 µA
I
LO
Output Leakage Current V
OUT
= GND to V
CC
1 µA
V
IL
Input Low Voltage 1V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
CC
+ 0.5 V
V
OL1
Output Low Voltage (V
CC
= +3.0V) I
OL
= 3.0 mA 0.4 V
V
OL2
Output Low Voltage (V
CC
= +1.8V) I
OL
= 1.5 mA 0.5 V
RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Typ Max Units
N
END
(3)
Endurance MIL-STD-883, Test Method 1033 100,000 Cycles/Byte
T
DR
(3)
Data Retention MIL-STD-883, Test Method 1008 100 Years
V
ZAP
(3)
ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
I
LTH
(3)(4)
Latch-up JEDEC Standard 17 100 mA
CAPACITANCE T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol Test Conditions Min Typ Max Units
C
I/O
(3)
Input/Output Capacitance (SDA) V
I/O
= 0V 8 pF
C
IN
(3)
Input Capacitance (SCL, WP, A0, A1) V
IN
= 0V 6 pF
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
CAT24WC256
3
Doc. No. 1031, Rev. F
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter V
CC
=1.8V - 6.0V V
CC
=2.5V - 6.0V V
CC
=3.0V - 5.5V
Min Max Min Max Min Max Units
F
SCL
Clock Frequency 100 400 1000 kHz
t
AA
SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 0.05 0.55 µs
and ACK Out
t
BUF
(2)
Time the Bus Must be Free Before 4.7 1.2 0.5 µs
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time 4.0 0.6 0.25 µs
t
LOW
Clock Low Period 4.7 1.2 0.6 µs
t
HIGH
Clock High Period 4.0 0.6 0.4 µs
t
SU:STA
Start Condition Setup Time 4.0 0.6 0.25 µs
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time 0 0 0 ns
t
SU:DAT
Data In Setup Time 100 100 100 ns
t
R
(2)
SDA and SCL Rise Time 1.0 0.3 0.3 µs
t
F
(2)
SDA and SCL Fall Time 300 300 100 ns
t
SU:STO
Stop Condition Setup Time 4.7 0.6 0.25 µs
t
DH
Data Out Hold Time 100 50 50 ns
t
WR
Write Cycle Time 10 10 10 ms
Power-Up Timing
(2)(3)
Symbol Parameter Min Typ Max Units
t
PUR
Power-Up to Read Operation 1 ms
t
PUW
Power-Up to Write Operation 1 ms
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