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CAT24C08YI-GT3

Part # CAT24C08YI-GT3
Description 8KB I2C SER EEPROM
Category IC
Availability In Stock
Qty 6
Qty Price
1 + $0.07481
Manufacturer Available Qty
ON Semiconductor
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
CAT24C01/02/04/08/16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
PIN CONFIGURATION FUNCTIONAL SYMBOL
FEATURES
Supports Standard and Fast I
2
C Protocol
1.8 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
TDFN (VP2)
V
CC
V
SS
SD
A
SCL
WP
CAT24Cxx
A
2
, A
1
, A
0
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I
2
C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
8
7
6
5
V
CC
WP
SCL
SDA
NC / A
2
/ A
2
/ A
2 /
A
2
NC / NC / NC / A
0 /
A
0
CAT24C16 / 08 / 04 / 02
/
01
NC / NC / A
1
/ A
1 /
A
1
V
SS
1
2
3
4
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A
0
, A
1
, A
2
Device Address Inputs
SDA Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
V
CC
Power Supply
V
SS
Ground
NC No Connect
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
TSOT-23 (TD)
5
4
WP
V
CC
SCL
V
SS
SDA
1
2
3
For Ordering Information details, see page 16.
CAT24C01/02/04/08/16
2
Doc. No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature -65°C to +150°C
Voltage on Any Pin with Respect to Ground
(2)
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS
(3)
Symbol Parameter Min Units
N
END
(4)
Endurance 1,000,000 Program/ Erase Cycles
T
DR
Data Retention 100 Years
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol Parameter Test Conditions Min Max Units
I
CCR
Read Current Read, f
SCL
= 400 kHz 1 mA
I
CCW
Write Current Write, f
SCL
= 400 kHz 1 mA
I
SB
Standby Current
All I/O Pins at GND or V
CC
1
μA
I
L
I/O Pin Leakage
Pin at GND or V
CC
1 μA
V
IL
Input Low Voltage -0.5 V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
CC
+ 0.5 V
V
OL1
Output Low Voltage
V
CC
2.5 V, I
OL
= 3.0 mA
0.4 V
V
OL2
Output Low Voltage V
CC
< 2.5 V, I
OL
= 1.0 mA 0.2 V
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol Parameter Conditions Max Units
C
IN
(3)
SDA I/O Pin Capacitance V
IN
= 0 V 8 pF
C
IN
(3)
Input Capacitance (other pins) V
IN
= 0 V 6 pF
I
WP
(5)
WP Input Current
V
IN
< V
IH,
V
CC
= 5.5 V 200
μA
V
IN
< V
IH,
V
CC
= 3.3 V 150
V
IN
< V
IH,
V
CC
= 1.8 V 100
V
IN
> V
IH
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci
-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
CAT24C01/02/04/08/16
3
Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C.
Symbol Parameter
Standard Fast
UnitsMin Max Min Max
F
SCL
Clock Frequency 100 400 kHz
t
HD:STA
START Condition Hold Time 4 0.6 μs
t
LOW
Low Period of SCL Clock 4.7 1.3 μs
t
HIGH
High Period of SCL Clock 4 0.6 μs
t
SU:STA
START Condition Setup Time 4.7 0.6 μs
t
HD:DAT
Data In Hold Time 0 0 μs
t
SU:DAT
Data In Setup Time 250 100 ns
t
R
SDA and SCL Rise Time 1000 300 ns
t
F
(2)
SDA and SCL Fall Time 300 300 ns
t
SU:STO
STOP Condition Setup Time 4 0.6 μs
t
BUF
Bus Free Time Between STOP and START 4.7 1.3 μs
t
AA
SCL Low to Data Out Valid 3.5 0.9 μs
t
DH
Data Out Hold Time 100 100 ns
T
i
(2)
Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
t
SU:WP
WP Setup Time 0 0 μs
t
HD:WP
WP Hold Time 2.5 2.5 μs
t
WR
Write Cycle Time 5 5
ms
t
PU
(2, 3)
Power-up to Ready Mode 1 1
ms
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels 0.2 x V
CC
to 0.8 x V
CC
Input Rise and Fall Times
50 ns
Input Reference Levels 0.3 x V
CC
, 0.7 x V
CC
Output Reference Levels 0.5 x V
CC
Output Load
Current Source: I
OL
= 3 mA (V
CC
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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