CAT24C01/02/04/08/16
8
Doc. No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/
W bit set
to ‘1’, the CAT24Cxx will interpret this as a request for
data residing at the current byte address in memory.
The CAT24Cxx will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24Cxx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read opera
-
tion. The Master device first performs a ‘dummy’ write
operation by sending the START condition, slave ad-
dress and byte address of the location it wishes to read.
After the CAT24Cxx acknowledges the byte address,
the Master device resends the START condition and
the slave address, this time with the R/W bit set to one.
The CAT24Cxx then responds with its acknowledge and
sends the requested data byte. The Master device does
not acknowledge the data (NoACK) but will generate a
STOP condition (Figure 10).
Sequential Read
If during a Read session, the Master acknowledges the 1
st
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure
11). In contrast to Page Write, during Sequential Read
the address count will automatically increment to and
then wrap-around at end of memory (rather than end
of page). In the CAT24C01, the internal address count
will not wrap around at the end of the 128 byte memory
space.
