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AD7716BSZ

Part # AD7716BSZ
Description ADC Single Delta-Sigma 570ksps 22-bit Serial 44-Pin MQFP -
Category IC
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Analog Devices
Date Code: 1010
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD7716
a
LC
2
MOS
22-Bit Data Acquisition System
There are 22 bits of data corresponding to the analog input.
Two bits contain the channel address and 3 bits are the device
address. Thus, each channel in a 32-channel system would have
a discrete 5-bit address. The device also has a CASCOUT pin
and a CASCIN pin that allow simple networking of multiple
devices.
The on-chip control register is programmed using the SCLK,
SDATA and
TFS pins. Three bits of the Control Register set
the digital filter cutoff frequency for the device. Selectable fre-
quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A
further 2 bits appear as outputs D
OUT
1 and D
OUT
2 and can be
used for controlling calibration at the front end. The device is
available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin
PLCC.
GENERAL DESCRIPTION
The AD7716 is a signal processing block for data acquisition
systems. It is capable of processing four channels with band-
widths of up to 584 Hz. Resolution is 22 bits and the usable
dynamic range varies from 111 dB with an input bandwidth of
36.5 Hz to 99 dB with an input bandwidth of 584 Hz.
The device consists of four separate A/D converter channels that
are implemented using sigma-delta technology. Sigma-delta
ADCs include on-chip digital filtering and, thus, the system
filtering requirements are eased.
Three address pins program the device address. This allows a
data acquisition system with up to 32 channels to be set up in a
simple fashion. The output word from the device contains 32
bits of data. One bit is determined by the state of the D
IN
1 in-
put and may be used, for example, in an ECG system with an
external pacemaker detect circuit to indicate that the output
word is invalid because of the presence of a pacemaker pulse.
FUNCTIONAL BLOCK DIAGRAM
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
CONTROL
REGISTER
CLOCK
GENERATION
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
CLKOUTCLKIN
V
REF
AGND DGND
D
IN
1
D
OUT
1
D
OUT
2
MODE
CASCIN
CASCOUT
SDATA
SCLK
TFS
RFS
DRDY
A
IN
1
A
IN
2
A
IN
3
A
IN
4
AV
DD
DV
DD
AV
SS
A0 A1 A2
RESET
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
AD7716
FEATURES
22-Bit Sigma-Delta ADC
Dynamic Range of 105 dB (146 Hz Input)
60.003% Integral Nonlinearity
On-Chip Low-Pass Digital Filter
Cutoff Programmable from 584 Hz to 36.5 Hz
Linear Phase Response
Five Line Serial I/O
Twos Complement Coding
Easy Interface to DSPs and Microcomputers
Software Control of Filter Cutoff
65 V Supply
Low Power Operation: 50 mW
APPLICATIONS
Biomedical Data Acquisition
ECG Machines
EEG Machines
Process Control
High Accuracy Instrumentation
Seismic Systems
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD7716–SPECIFICATIONS
1, 2
(f
CLKIN
= 8 MHz; MODE Pin Is High (Slave Mode Operation); AV
DD
= DV
DD
= +5 V
6 5%; AV
SS
= –5 V 6 5%; AGND = DGND = 0 V; V
REF
= 2.5 V; Filter Cutoff = 146 Hz; Noise Measurement Bandwidth = 146 Hz; A
IN
Source
Resistance = 750 V
2
with 1 nF to AGND at each A
IN
. T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter B Version Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution 22 Bits
Integral Linearity Error 0.003 % FSR typ Guaranteed No Missed Codes to 21 Bits
3
0.006 % FSR max
Gain Error 1 % FSR max
Gain Match Between Channels 0.5 % FSR max
Gain TC 30 µV/°C typ
Offset Error 0.2 % FSR max
Offset Match Between Channels 0.1 % FSR max
Offset TC 4 µV/°C typ
Noise 11 µV rms max See Table I for Typical Noise Performance vs. Programmed
Cutoff Frequency
DYNAMIC PERFORMANCE
Sampling Rate f
CLKIN
/14 570 kHz for f
CLKIN
= 8 MHz
Output Update Rate f
CLKIN
/(14 3 256 3 2
N
) N Is Decimal Equivalent of FC2, FC1, FC0 in Control Register
Filter Cutoff Frequency f
CLKIN
/(3.81 3 14 3 256 3 2
N
)
Settling Time (3 3 14 3 256 3 2
N
/f
CLKIN
)
Usable Dynamic Range
4
See Table I
Total Harmonic Distortion –90 dB typ Input Frequency = 35 Hz
–100 dB typ A
IN
= ±10 mV p-p
Absolute Group Delay
3
(3 3 14 3 256 3 2
N
)/2f
CLKIN
Differential Group Delay
3
10 ns typ
Channel-to-Channel Isolation –85 dB typ Feedthrough from Any One Channel to the Other Three, with
35 Hz Full-Scale Sine Wave Applied to that Channel
ANALOG INPUT
Input Range ±2.5 Volts
Input Capacitance 10 pF typ
Input Bias Current 1 nA typ
LOGIC INPUTS
V
INH
, Input High Voltage 2.4 V min
V
INL
, Input Low Voltage 0.8 V max
I
IN
, Input Current
SDATA, RFS +10/-130 µA max Internal 50 k Pull-Up Resistors
TFS +10/-650 µA max Internal 10 k Pull-Up Resistor
All Other Inputs ±10 µA max
C
IN
, Input Capacitance
3
10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 2.4 V min |I
OUT
| 40 µA
V
OL
, Output Low Voltage 0.4 V max |I
OUT
| 1.6 mA
POWER SUPPLIES
Reference Input 2.4/2.6 V min/V max
AV
DD
4.75/5.25 V min/V max
DV
DD
4.75/5.25 V min/V max
AV
SS
–4.75/–5.25 V min/V max
I
DD
7.5 mA max 4.8 mA typ
I
SS
2.5 mA max 1.8 mA typ
Power Consumption 50 mW max 35 mW typ
Power Supply Rejection
5
–70 dB typ
NOTES
1
Operating temperature ranges as follows : B Version; –40°C to +85°C.
2
The A
IN
pins present a very high impedance dynamic load which varies with clock frequency.
3
Guaranteed by design and characterization. Digital filter has linear phase.
4
Usable dynamic range is guaranteed by measuring noise and relating this to the full-scale input range.
5
100 mV p-p, 120 Hz sine wave applied to each supply.
Specifications subject to change without notice.
REV. A–2–
REV. A
–3–
AD7716
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
Programmed Cutoff Output Update Usable Dynamic RMS Noise Filter Settling Time to Absolute Group
N Frequency (Hz) Rate (Hz) Range (dB) (mV) 60.0007% FS (ms) Delay (ms)
0 584 2232 99 21 1.35 0.675
1 292 1116 102 14 2.7 1.35
2 146 558 105 10 5.4 2.7
3 73 279 108 7 10.8 5.4
4 36.5 140 111 5 21.6 10.8
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V 6 5%; AV
SS
= –5 V 6 5%; AGND =
DGND = 0 V; f
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
DD
; unless otherwise noted)
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
1/f
CLKIN
ns min SCLK Period
t
2
77 ns min SCLK Width
t
3
30 ns min TFS Setup Time
t
4
20 ns min SDATA Setup Time
t
5
10 ns min SDATA Hold Time
t
6
20 ns min TFS Hold Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
CLKIN Duty Cycle range is 40% to 60%.
200µA
I
OH
+2.1V
TO
OUTPUT
PIN
1.6mA
C
L
50pF
I
OL
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
DB4
(DB12)
DB3
(DB11)
DB2
(DB10)
DB1
(DB9)
DB0
(DB8)
DB5
(DB13)
DB6
(DB14)
DB7
(DB15)
t
2
SCLK (I)
SDATA (I)
TFS (I)
t
2
t
5
t
4
t
3
t
6
t
1
Figure 2. Control Register Timing Diagram
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