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AD7715AR-3

Part # AD7715AR-3
Description ADC SGL DELTA-SIGMA 19.2KSPS16BIT SERL 16SOIC W - Rail/Tu
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

FUNCTIONAL BLOCK DIAGRAM
PGABUFFER
CHARGE BALANCING
A/D CONVERTER
SIGMA-DELTA
MODULATOR
DIGITAL
FILTER
REF IN(–) REF IN(+)
AV
DD
DV
DD
A = 1–128
MCLK IN
MCLK OUT
RESET
AIN(+)
AIN(–)
SERIAL
INTERFACE
REGISTER BANK
SCLK
CS
DIN
DOUT
DRDY
CLOCK
GENERATION
AGND
DGND
AD7715
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
3 V/5 V, 450 A
16-Bit, Sigma-Delta ADC
AD7715*
FEATURES
Charge-Balancing ADC
16 Bits No Missing Codes
0.0015% Nonlinearity
Programmable Gain Front End
Gains of 1, 2, 32 and 128
Differential Input Capability
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Ability to Buffer the Analog Input
3 V (AD7715-3) or 5 V (AD7715-5) Operation
Low Supply Current: 450␣ A max @ 3␣ V Supplies
Low-Pass Filter with Programmable Output Update
16-Lead SOIC/DIP/TSSOP
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
50␣ µW typ. The part is available in a 16-lead, 0.3 inch-wide,
plastic dual-in-line package (DIP) as well as a 16-lead 0.3 inch-
wide small outline (SOIC) package and a 16-lead TSSOP package.
PRODUCT HIGHLIGHTS
1. The AD7715 consumes less than 450␣ µA in total supply
current at 3 V supplies and 1␣ MHz master clock, making it
ideal for use in low-power systems. Standby current is less
than 10␣ µA.
2. The programmable gain input allows the AD7715 to accept
input signals directly from a strain gage or transducer remov-
ing a considerable amount of signal conditioning.
3. The AD7715 is ideal for microcontroller or DSP processor
applications with a three-wire serial interface reducing the
number of interconnect lines and reducing the number of
opto-couplers required in isolated systems. The part con-
tains on-chip registers which allow software control over
output update rate, input gain, signal polarity and calibration
modes.
4. The part features excellent static performance specifications
with 16-bits no missing codes, ±0.0015% accuracy and low
rms noise (<550␣ nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration op-
tions, which remove zero-scale and full-scale errors.
GENERAL DESCRIPTION
The AD7715 is a complete analog front end for low frequency
measurement applications. The part can accept low level input
signals directly from a transducer and outputs a serial digital
word. It employs a sigma-delta conversion technique to realize
up to 16 bits of no missing codes performance. The input signal
is applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is pro-
cessed by an on-chip digital filter. The first notch of this digital
filter can be programmed via the on-chip control register allow-
ing adjustment of the filter cutoff and output update rate.
The AD7715 features a differential analog input as well as a dif-
ferential reference input. It operates from a single supply (+3␣ V
or +5␣ V). It can handle unipolar input signal ranges of 0 mV to
+20␣ mV, 0 mV to +80␣ mV, 0 V to +1.25␣ V and 0 V to +2.5␣ V.
It can also handle bipolar input signal ranges of ±20␣ mV, ± 80␣ mV,
±1.25␣ V and ±2.5␣ V. These bipolar ranges are referenced to
the negative input of the differential analog input. The AD7715
thus performs all signal conditioning and conversion for a single-
channel system.
The AD7715 is ideal for use in smart, microcontroller or DSP
based systems. It features a serial interface that can be config-
ured for three-wire operation. Gain settings, signal polarity and
update rate selection can be configured in software using the
input serial port. The part contains self-calibration and system
calibration options to eliminate gain and offset errors on the
part itself or in the system.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
*Protected by U.S. Patent No: 5,134,401.
See page 30 for data sheet index.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Parameter A Version
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 16 Bits min Guaranteed by Design. Filter Notch 60␣ Hz
Output Noise See Tables V to VIII Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ±0.0015 % of FSR max Filter Notch 60␣ Hz
Unipolar Offset Error See Note 2
Unipolar Offset Drift
3
0.5 µV/°C typ
Bipolar Zero Error See Note 2
Bipolar Zero Drift
3
0.5 µV/°C typ
Positive Full-Scale Error
4
See Note 2
Full-Scale Drift
3, 5
0.5 µV/°C typ
Gain Error
6
See Note 2
Gain Drift
3, 7
0.5 ppm of FSR/°C typ
Bipolar Negative Full-Scale Error
2
±0.0015 % of FSR max Typically ±0.0004%
Bipolar Negative Full-Scale Drift
3
1 µV/°C typ For Gains of 1 and 2
0.6 µV/°C typ For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR) 90 dB min at DC. Typically 102 dB
Normal-Mode 50 Hz Rejection
8
98 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
8
98 dB min For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
8
150 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
8
150 dB min For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f
NOTCH
Common-Mode Voltage Range
9
AGND to AV
DD
V min to V max AIN for BUF Bit of Setup Register = 0 and REF IN
Absolute AIN/REF IN Voltage
8
AGND – 30 mV V min AIN for BUF Bit of Setup Register = 0 and REF IN
AV
DD
+ 30␣ mV V max
Absolute/Common-Mode AIN Voltage
9
AGND + 50␣ mV V min BUF Bit of Setup Register = 1
AV
DD
– 1.5␣ V V max
AIN DC Input Current
8
1 nA max
AIN Sampling Capacitance
8
10 pF max
AIN Differential Voltage Range
10
0 to +V
REF
/GAIN
11
nom Unipolar Input Range (B/U Bit of Setup Register = 1)
±V
REF
/GAIN nom Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, f
S
GAIN × f
CLK␣ IN
/64 For Gains of 1 and 2
f
CLK␣ IN
/8 For Gains of 32 and 128
REF IN(+) – REF IN(–) Voltage +2.5 V nom ±1% for Specified Performance. Functional with
Lower V
REF
REF IN Input Sampling Rate, f
S
f
CLK IN
/64
LOGIC INPUTS
Input Current ±10 µA max
All Inputs Except MCLK IN
V
INL
, Input Low Voltage 0.8 V max DV
DD
= +5␣ V
V
INL
, Input Low Voltage 0.4 V max DV
DD
= +3.3␣ V
V
INH
, Input High Voltage 2.4 V min DV
DD
= +5 V
V
INH
, Input High Voltage 2.0 V min
MCLK IN Only
V
INL
, Input Low Voltage 0.8 V max DV
DD
= +5␣ V
V
INL
, Input Low Voltage 0.4 V max DV
DD
= +3.3␣ V
V
INH
, Input High Voltage 3.5 V min DV
DD
= +5␣ V
V
INH
, Input High Voltage 2.5 V min DV
DD
= +3.3␣ V
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 800␣ µA Except for MCLK OUT
12
. DV
DD
= +5␣ V
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 100␣ µA Except for MCLK OUT
12
. DV
DD
= +3.3␣ V
V
OH
, Output High Voltage 4.0 V min I
SOURCE
= 200 µA Except for MCLK OUT
12
. DV
DD
= +5␣ V
V
OH
, Output High Voltage DV
DD
– 0.6 V V min I
SOURCE
= 100 µA Except for MCLK OUT
12
. DV
DD
= +3.3␣ V
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
13
9 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
AD7715-5–SPECIFICATIONS
(AV
DD
= +5␣ V, DV
DD
= +3␣ V or +5␣ V, REF IN(+) = +2.5␣ V; REF␣ IN(–) = AGND;
f
CLK IN
= 2.4576␣ MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. C–2–
Parameter A Version
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 16 Bits min Guaranteed by Design. Filter Notch 60␣ Hz
Output Noise See Tables IX to XII Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ±0.0015 % of FSR max Filter Notch 60␣ Hz
Unipolar Offset Error See Note 2
Unipolar Offset Drift
3
0.2 µV/°C typ
Bipolar Zero Error See Note 2
Bipolar Zero Drift
3
0.2 µV/°C typ
Positive Full-Scale Error
4
See Note 2
Full-Scale Drift
3, 5
0.2 µV/°C typ
Gain Error
6
See Note 2
Gain Drift
3, 7
0.2 ppm of FSR/°C typ
Bipolar Negative Full-Scale Error
2
±0.003 % of FSR max Typically ±0.0004%
Bipolar Negative Full-Scale Drift
3
1 µV/°C typ For Gains of 1 and 2
0.6 µV/°C typ For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR) 90 dB min at DC. Typically 102 dB
Normal-Mode 50 Hz Rejection
8
98 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
8
98 dB min For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
8
150 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
8
150 dB min For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f
NOTCH
Common-Mode Voltage Range
9
AGND to AV
DD
V min to V max AIN for BUF Bit of Setup Register = 0 and REF IN
Absolute AIN/REF IN Voltage
8
AGND – 30 mV V min AIN for BUF Bit of Setup Register = 0 and REF IN
AV
DD
+ 30␣ mV V max
Absolute/Common-Mode AIN Voltage
9
AGND + 50␣ mV V min BUF Bit of Setup Register = 1
AV
DD
– 1.5␣ V V max
AIN DC Input Current
8
1 nA max
AIN Sampling Capacitance
8
10 pF max
AIN Differential Voltage Range
10
0 to +V
REF
/GAIN
11
nom Unipolar Input Range (B/U Bit of Setup Register = 1)
±V
REF
/GAIN nom Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, f
S
GAIN × f
CLK␣ IN
/64 For Gains of 1 and 2
f
CLK␣ IN
/8 For Gains of 32 and 128
REF IN(+) – REF IN(–) Voltage +1.25 V nom ±1% for Specified Performance. Functional with Lower V
REF
REF IN Input Sampling Rate, f
S
f
CLK IN
/64
LOGIC INPUTS
Input Current ±10 µA max
All Inputs Except MCLK IN
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 2.0 V min
MCLK IN Only
V
INL
, Input Low Voltage 0.4 V max
V
INH
, Input High Voltage 2.5 V min
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 100␣ µA Except for MCLK OUT
12
V
OH
, Output High Voltage DV
DD
– 0.6 V min I
SOURCE
= 100 µA Except for MCLK OUT
12
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
13
9 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
AD7715
AD7715-3–SPECIFICATIONS
(AV
DD
= +3␣ V, DV
DD
= +3 V, REF IN (+) = +1.25␣ V;
REF␣ IN(–) = AGND; f
CLK IN
= 2.4576␣ MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
–3–
REV. C
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