Parameter A, S Versions
1
Units Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz
22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz
Output Noise See Tables I & II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ +25°C ±0.0015 % FSR max Filter Notches ≤ 60 Hz
T
MIN
to T
MAX
±0.003 % FSR max Typically ±0.0003%
Positive Full-Scale Error
2, 3
See Note 4 Excluding Reference
Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2
See Note 4
Unipolar Offset Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
See Note 4
Bipolar Zero Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error
2
@ +25°C ±0.003 % FSR max Excluding Reference
T
MIN
to T
MAX
±0.006 % FSR max Typically ±0.0006%
Bipolar Negative Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Normal-Mode 50 Hz Rejection
6
100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
6
100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
NOTCH
AIN1/REF IN
DC Input Leakage Current
@ +25°C
6
10 pA max
T
MIN
to T
MAX
1 nA max
Sampling Capacitance
6
20 pF max
Common-Mode Rejection (CMR) 100 dB min At DC
Common-Mode 50 Hz Rejection
6
150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
6
150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
NOTCH
Common-Mode Voltage Range
7
V
SS
to AV
DD
V min to V max
Analog Inputs
8
Input Sampling Rate, f
S
See Table III
AIN1 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 to +V
REF
10
V max Unipolar Input Range (B/U Bit of Control Register = 1)
±V
REF
V max Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 to + 4 × V
REF
10
V max Unipolar Input Range (B/U Bit of Control Register = 1)
±4 × V
REF
V max Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 DC Input Impedance 30 kΩ
AIN2 Gain Error
11
±0.05 % typ Additional Error Contributed by Resistor Attenuator
AIN2 Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator
AIN2 Offset Error
11
10 mV max Additional Error Contributed by Resistor Attenuator
AIN2 Offset Drift 20 µV/°C typ
Reference Inputs
REF IN(+) – REF IN(–) Voltage
12
+2.5 to +5 V min to V max For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
Input Sampling Rate, f
S
f
CLK IN
/256
NOTES
1
Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
8
The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV
DD
+ 30 mV or more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the STATIC PERFORMANCE section.
12
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
–2– REV. E
(AV
DD
= +5␣ V ⴞ 5%; DV
DD
= +5␣ V ⴞ 5%; V
SS
= 0␣ V or –5 V ⴞ 5%; REF IN(+) = +2.5␣ V;
REF IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise stated. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7712–SPECIFICATIONS
