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AD532SD/883B

Part # AD532SD/883B
Description ANLG MLTPLR/DIVIDER 4BIT 14CDIP - Rail/Tube
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $104.39000



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD532
Rev. D | Page 3 of 16
SPECIFICATIONS
At 25°C, V
S
= ±15 V, R ≥ 2 kΩ V
OS
grounded, unless otherwise noted.
Table 1.
AD532J AD532K AD532S
Model
Conditions
Min Typ Max Min Typ Max Min Typ Max Unit
MULTIPLIER PERFORMANCE
Transfer Function
V
YYXX
10
)()(
2121
V
YYXX
10
)()(
2121
V
YYXX
10
)()(
2121
Total Error 10 V ≤ X, Y ≤ +10 V ±1.5 ±2.0 ±0.7 ±1.0 ±0.5 ±1.0 %
T
A
= Minimum to Maximum ±2.5 ±1.5 ±4.0 %
Total Error vs. Temperature ±0.04 ±0.03 ±0.01 ±0.04 %/°C
Supply Rejection ±15 V ±10% ±0.05 ±0.05 ±0.05 %/%
Nonlinearity, X X = 20 V p-p, Y = 10 V ± 0.8 ±0.5 ±0.5 %
Nonlinearity, Y Y = 20 V p-p, X = 10 V ±0.3 ±0.2 ±0.2 %
Feedthrough, X Y nulled, X = 20 V p-p 50 Hz 50 200 30 100 30 100 mV
Feedthrough, Y (X Nulled, 30 150 25 80 25 80 mV
Y = 20 V p-p 50 Hz)
Feedthrough vs. Temperature 2.0 1.0 1.0 mV p-p/°C
Feedthrough vs. Power Supply ±0.25 ±0.25 ±0.25 mV/%
DYNAMICS
Small Signal BW V
OUT
= 0.1 rms 1 1 1 MHz
1% Amplitude Error 75 75 75 kHz
Slew Rate V
OUT
20 p-p 45 45 45 V/μs
Settling Time to 2%, ΔV
OUT
= 20 V 1 1 1 μs
NOISE
Wideband Noise 0.6 0.6 0.6 mV (rms)
f = 5 Hz to 10 kHz
f = 5 Hz to 5 MHz 3.0 3.0 3.0 mV (rms)
OUTPUT
Voltage Swing ±10 ±13 ±10 ±13 ±10 ±13 V
Impedance f ≤ 1 kHz 1 1 1
Offset Voltage ±40 ±30 ±30 mV
Offset Voltage vs. Temperature 0.7 0.7 2.0 mV/°C
Offset Voltage vs. Supply ±2.5 ±2.5 ±2.5 mV/%
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range
Differential or CM
operating differential
±10 ±10 ±10 V
CMRR 40 50 50 dB
Input Bias Current
X, Y Inputs 3 1.5 4 1.5 4 μA
X, Y Inputs T
MIN
to T
MAX
10 8 8 ±15 μA
Z Input ±10 ±5 ±15 ±5 μA
Z Input T
MIN
to T
MAX
±30 ±25 ±25 μA
Offset Current ±0.3 ±0.1 ±0.1 μA
Differential Resistance 10 10 10 MΩ
DIVIDER PERFORMANCE
Transfer Function X
l
> X
2
10 V Z/(X
1
− X
2
) 10 V Z/(X
1
− X
2
) 10 V Z/(X
1
− X
2
)
Total Error
V
X
= −10 V, −10 V ≤ V
Z
+10 V
±2 ±1 ±1 %
V
X
= 1 V, 10 V ≤ V
Z
+10 V
±4 ±3 ±3 %
AD532
Rev. D | Page 4 of 16
AD532J AD532K AD532S
Model
Conditions
Min Typ Max Min Typ Max Min Typ Max Unit
SQUARE PERFORMANCE
V
XX
10
)(
2
21
V
XX
10
)(
2
21
V
XX
10
)(
2
21
Transfer Function
Total Error ±0.8 ±0.4 ±0.4 %
SQUARE ROOTER PERFORMANCE
Transfer Function
−√
10 V Z
−√
10 V Z
−√
10 V Z
Total Error 0 V ≤ V
Z
≤ 10 V ±1.5 ±1.0 ±1.0 %
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ±15 ±15 V
Operating ±10 ±18 ±10 ±18 ±10 ±22 V
Supply Current
Quiescent 4 6 4 6 4 6 mA
AD532
Rev. D | Page 5 of 16
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
H-10A 150 25 °C/W
E-20A 85 22 °C/W
D-14 85 22 °C/W
CHIP DIMENSIONS AND BONDING DIAGRAM
Contact factory for latest dimensions.
Dimensions are shown in inches and (mm).
Figure 2.
ESD CAUTION
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