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AD5321BRM

Part # AD5321BRM
Description IC DAC 12BIT 2.5V 2-WIRE 8-MSOP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5301/AD5311/AD5321*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
+2.5 V to +5.5 V, 120 A, 2-Wire Interface,
Voltage Output 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
RESISTOR
NETWORK
BUFFER
V
OUT
DAC
REGISTER
POWER-DOWN
LOGIC
AD5301/AD5311/AD5321
V
DD
SCL
A0
GND
A1*
REF
POWER-ON
RESET
PD*
SDA
*AVAILABLE ON 8-LEAD VERSION ONLY
8-/10-/12-BIT
DAC
INTERFACE
LOGIC
FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead SOIC Packages
Micropower Operation: 120 A @ 3 V
2-Wire (I
2
C
®
Compatible) Serial Interface
Data Readback Capability
+2.5 V to +5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
On-Chip Rail-to-Rail Output Buffer Amplifier
Three Power-Down Functions
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit
buffered voltage-output DACs that operate from a single +2.5 V
to +5.5 V supply consuming 120 µA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/µs. It uses a 2-wire (I
2
C compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on-reset circuit, which ensures that
the DAC output powers-up to zero volts and remains there until
a valid write takes place. The parts contain a power-down feature
which reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V
reducing to 1 µW in all power-down modes.
I
2
C is a registered trademark of Philips Corporation.
*Protected by U.S. Patent No. 5684481, other patent pending.
REV. 0–2–
AD5301/AD5311/AD5321–SPECIFICATIONS
(V
DD
= +2.5 V to +5.5 V; R
L
= 2 k to GND;
C
L
= 200 pF to GND; All specifications T
MIN
to T
MAX
unless otherwise noted.)
B Version
2
Parameter
1
Min Typ Max Units Conditions/Comments
DC PERFORMANCE
3, 4
AD5301
Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic by Design Over All Codes
AD5311
Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic by Design Over All Codes
AD5321
Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed Monotonic by Design Over All Codes
Zero Code Error +5 +20 mV All Zeros Loaded to DAC, See Figure 9
Full-Scale Error ±0.15 ±1.25 % of FSR All Ones Loaded to DAC, See Figure 9
Gain Error ±0.15 ±1 % of FSR
Zero Code Error Drift
5
–20 µV/°C
Gain Error Drift
5
–5 ppm of FSR/°C
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage 0.001 V min This is a measure of the minimum and maximum drive
Maximum Output Voltage V
DD
0.001 V max capability of the output amplifier.
DC Output Impedance 1
Short Circuit Current 50 mA V
DD
= +5 V
20 mA V
DD
= +3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V
DD
= +5␣ V
6 µs Coming Out of Power-Down Mode. V
DD
= +3␣ V
LOGIC INPUTS (A0, A1, PD)
5
Input Current ±1 µA
V
IL
, Input Low Voltage 0.8 V V
DD
= +5 V ± 10%
0.6 V V
DD
= +3 V ± 10%
0.5 V V
DD
= +2.5 V
V
IH
, Input High Voltage 2.4 V V
DD
= +5 V ± 10%
2.1 V V
DD
= +3 V ± 10%
2.0 V V
DD
= +2.5 V
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)
5
V
IH
, Input High Voltage 0.7 V
DD
V
DD
+ 0.3 V
V
IL
, Input Low Voltage –0.3 0.3 V
DD
V
I
IN
, Input Leakage Current ±1 µAV
IN
= 0 V to V
DD
V
HYST
, Input Hysteresis 0.05 V
DD
V
C
IN
, Input Capacitance 6 pF
Glitch Rejection
6
50 ns Pulsewidth of Spike Suppressed
LOGIC OUTPUT (SDA)
5
V
OL
, Output Low Voltage 0.4 V I
SINK
= 3 mA
0.6 V I
SINK
= 6 mA
Three-State Leakage Current ±1 µA
Three-State Output Capacitance 6 pF
POWER REQUIREMENTS
V
DD
2.5 5.5 V I
DD
Specification Is Valid for All DAC Codes
I
DD
(Normal Mode) DAC Active and Excluding Load Current
V
DD
= +4.5 V to +5.5 V 150 250 µAV
IH
= V
DD
and V
IL
= GND
V
DD
= +2.5 V to +3.6 V 120 220 µAV
IH
= V
DD
and V
IL
= GND
I
DD
(Power-Down Mode)
V
DD
= +4.5 V to +5.5 V 0.2 1 µAV
IH
= V
DD
and V
IL
= GND
V
DD
= +2.5 V to +3.6 V 0.05 1 µAV
IH
= V
DD
and V
IL
= GND
NOTES
1
See Terminology.
2
Temperature ranges are as follows: B Version: –40°C to +105°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000).
5
Guaranteed by Design and Characterization, not production tested.
6
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
REV. 0
AD5301/AD5311/AD5321
–3–
AC CHARACTERISTICS
1
B Version
3
Parameter
2
Min Typ Max Units Conditions/Comments
Output Voltage Settling Time V
DD
= +5 V
AD5301 6 8 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311 7 9 µs 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5321 8 10 µs 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Change Glitch Impulse 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.3 nV-s
NOTES
1
See Terminology
2
Guaranteed by design and characterization, not production tested.
3
Temperature ranges are as follows: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1
Limit at T
MIN
, T
MAX
Parameter
2
(B Version) Units Conditions/Comments
f
SCL
400 kHz max SCL Clock Frequency
t
1
2.5 µs min SCL Cycle Time
t
2
0.6 µs min t
HIGH
, SCL High Time
t
3
1.3 µs min t
LOW
, SCL Low Time
t
4
0.6 µs min t
HD,STA
, Start/Repeated Start Condition Hold Time
t
5
100 ns min t
SU,DAT
, Data Setup Time
t
6
3
0.9 µs max t
HD,DAT
, Data Hold Time
0 µs min
t
7
0.6 µs min t
SU,STA
, Setup Time for Repeated Start
t
8
0.6 µs min t
SU,STO
, Stop Condition Setup Time
t
9
1.3 µs min t
BUF
, Bus Free Time Between a STOP Condition and a START Condition
t
10
300 ns max t
R
, Rise Time of Both SCL and SDA when Receiving
0 ns min May be CMOS Driven
t
11
250 ns max t
F
, Fall Time of SDA when Receiving
300 ns max t
F
, Fall Time of Both SCL and SDA when Transmitting
20 + 0.1C
b
4
ns min
C
b
400 pF max Capacitive Load for Each Bus Line
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization, not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH MIN
of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
(V
DD
= +2.5 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; All specifications T
MIN
to T
MAX
unless
otherwise noted.)
(V
DD
= +2.5 V to +5.5 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
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