AMP 10256-8

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Technical Document


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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-02069 Rev. *F Revised July 13, 2004
Ayama™ 10000
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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F Page 2 of 153
TABLE OF CONTENTS
1.0 FEATURES ....................................................................................................................................10
2.0 OVERVIEW ....................................................................................................................................11
3.0 DEVICE ARCHITECTURE OVERVIEW .........................................................................................13
3.1 Data Array, Mask Array and Table Widths ................................................................................13
3.2 Data and Mask Addressing .......................................................................................................14
3.3 Successful Search and Multiple Match Arbitration ....................................................................14
4.0 SIGNALS DESCRIPTION ..............................................................................................................15
5.0 FUNCTIONAL DESCRIPTION .......................................................................................................18
5.1 Modes of Operation ..................................................................................................................18
5.1.1 Non-Enhanced Mode ......................................................................................................................18
5.1.2 Enhanced Mode .............................................................................................................................. 18
5.1.2.1 Mini-Key ........................................................................................................................................................ 19
5.1.2.2 Soft Priority ................................................................................................................................................... 19
5.1.2.3 Parity ............................................................................................................................................................. 20
5.1.2.4 MultiSearch ................................................................................................................................................... 22
5.1.2.5 Enhanced Learn Operation .......................................................................................................................... 23
5.2 I/O Interfaces ............................................................................................................................ 23
5.2.1 ASIC Interface ................................................................................................................................. 24
5.2.2 SRAM Interface ...............................................................................................................................24
5.2.3 Cascade Interface ........................................................................................................................... 24
5.3 Output Signals Default Driver/Last Device Designation (LRAM and LDEV) .............................25
5.4 Registers ...................................................................................................................................25
5.4.1 Comparand Register (CMPR) .........................................................................................................26
5.4.2 Global Mask Register (GMR) .......................................................................................................... 26
5.4.3 Search Successful Register (SSR) ................................................................................................. 27
5.4.4 Command Register (COMMAND) ................................................................................................... 28
5.4.5 Information Register (INFO) ............................................................................................................ 30
5.4.6 Read Burst Address Register (RBURREG) ....................................................................................30
5.4.7 Write Burst Address Register (WBURREG) .................................................................................... 31
5.4.8 Next-free Address Register (NFA) .................................................................................................. 31
5.4.9 Configuration Register (CONFIG) ................................................................................................... 32
5.4.10 Hardware Register (HARDWARE) ................................................................................................33
5.4.11 Parity Control Register (PARITY) ..................................................................................................34
5.4.12 Control Register (CPR[0:15]) ........................................................................................................ 35
5.4.13 Search Result Register (SRR[15:0]) ............................................................................................. 36
5.4.14 Block Mini-Key Register (BMR) ..................................................................................................... 37
5.4.15 Block Priority Register (BPR) ........................................................................................................ 38
5.4.16 Block Parity Register (BPAR) ........................................................................................................39
5.4.17 Block NFA Register (BNFA) .......................................................................................................... 39
5.4.18 Block Priority Register Aliases (BPRA) ......................................................................................... 40
5.5 Multi-Hit Description ..................................................................................................................41
5.6 Clocks .......................................................................................................................................42
5.7 Phase-Locked Loop ..................................................................................................................43
5.8 Pipeline Latency ........................................................................................................................ 43
5.9 DQ Bus Encoding of Ayama 10000 Address Space .................................................................43
5.9.1 Addressing the Data Array, Mask Array and External SRAM ......................................................... 44
5.9.2 Addressing the Internal Registers ...................................................................................................45
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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F Page 3 of 153
TABLE OF CONTENTS (continued)
5.10 Depth Cascading .................................................................................................................... 45
5.10.1 Depth Cascading up to Eight Devices in One Block ..................................................................... 45
5.10.2 Depth Cascading up to 31 Devices in 4 Blocks ............................................................................47
5.10.3 Depth Cascading for a FULL Signal ..............................................................................................47
5.11 Device Selection in a Cascaded System ................................................................................48
5.12 Power-up Sequence ...............................................................................................................49
6.0 OPERATIONS AND TIMING DIAGRAMS .....................................................................................50
6.1 Command Encoding .................................................................................................................50
6.2 Command Bus Parameters ....................................................................................................... 50
6.2.1 Non-Enhanced Mode (EMODE = 0) ...............................................................................................50
6.2.2 Enhanced Mode (EMODE = 1) with MultiSearch Disabled (MSE = 0) ............................................ 51
6.2.3 Enhanced Mode (EMODE = 1) with MultiSearch Enabled (MSE = 1) ............................................ 51
6.3 Read Command ........................................................................................................................51
6.3.1 Single Read .....................................................................................................................................52
6.3.2 Burst Read ......................................................................................................................................52
6.3.3 Read Parity .....................................................................................................................................53
6.4 Write Command ........................................................................................................................ 53
6.4.1 Single Write ..................................................................................................................................... 54
6.4.2 Burst Write ...................................................................................................................................... 54
6.4.3 Parallel Write ...................................................................................................................................55
6.5 Search Command .....................................................................................................................56
6.5.1 Mixed-size Single Searches with One Device on Tables Configured with Different Widths ........... 56
6.5.2 Mixed-size Multi Searches with One Device on Tables Configured with Different Widths .............. 58
6.5.3 72-bit Single Search for 1 device or cascade up to eight devices ...................................................60
6.5.4 72-bit MultiSearch for One Device or Cascade Up to Eight Devices .............................................. 65
6.5.5 144-bit Single Search for Cascade Up to 31 Devices ..................................................................... 72
6.5.6 576-bit Single Search for One Device or Cascade up to Eight Devices ......................................... 85
6.5.7 576-bit MultiSearch for One Device or Cascade up to Eight Devices ............................................. 89
6.5.8 Mixed-size Single Searches with 31 Devices on Tables Configured with Different Widths ............95
6.5.9 Mixed-size Multi Searches with 8 Devices on Tables Configured with Different Widths ............... 107
6.6 Learn Command ..................................................................................................................... 113
6.6.1 Non-Enhanced Mode .................................................................................................................... 113
6.6.2 Enhanced Mode ............................................................................................................................ 114
6.6.3 Learn Operation on Depth-Cascaded Table .................................................................................117
6.7 SRAM PIO Access ..................................................................................................................121
6.7.1 SRAM Read with a Table of One Device ......................................................................................121
6.7.2 SRAM Read with a Table of up to Eight Devices .......................................................................... 122
6.7.3 SRAM Read with a Table of up to 31 Devices .............................................................................. 125
6.7.4 SRAM Write with a Table of One Device ...................................................................................... 127
6.7.5 SRAM Write with a Table of up to Eight Devices ..........................................................................129
6.7.6 SRAM Write with Table(s) Consisting of up to 31 Devices ........................................................... 131
6.8 Timing Sequences for Back-to-Back Operations ....................................................................133
6.9 Full Signal Timing Diagram .....................................................................................................134
7.0 JTAG (IEEE 1149.1) .....................................................................................................................135
8.0 POWER CONSUMPTION ............................................................................................................136
9.0 ELECTRICAL SPECIFICATIONS ................................................................................................137
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