User's Guide

SLUU526–August 2011

Using the TPS51916EVM-746 Complete DDR2, DDR3,

DDR3L, and DDR4 Memory Power Solution Synchronous

Buck Controller, 2-A LDO, Buffered Reference

The TPS51916EVM-746 evaluation module (EVM) allows users to evaluate the performance of the

TPS51916 low-dropout (LDO) regulator. The TPS51916 provides a complete power supply for DDR2,

DDR3, DDR3L, and DDR4 memory system in the lowest total cost and minimum space. TPS51916

integrates a synchronous buck controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered,

low-noise reference (VTTREF).

Contents

1 Description ................................................................................................................... 3

1.1 Typical Applications ................................................................................................ 3

1.2 Features ............................................................................................................. 3

2 Electrical Performance Specifications .................................................................................... 3

3 Schematic .................................................................................................................... 5

4 Test Setup ................................................................................................................... 6

4.1 Test Equipment ..................................................................................................... 6

4.2 Recommended Test Setup ....................................................................................... 7

5 Configurations ............................................................................................................... 8

5.1 S3, S5 Enable Selection .......................................................................................... 8

6 Test Procedure .............................................................................................................. 8

6.1 Line/Load Regulation and Efficiency Measurement Procedure .............................................. 8

6.2 List of Test Points .................................................................................................. 8

6.3 Equipment Shutdown .............................................................................................. 9

7 Performance Data and Typical Characteristic Curves ................................................................. 9

7.1 DDR3 VDDQ Efficiency ........................................................................................... 9

7.2 DDR3 VDDQ Load Regulation .................................................................................. 10

7.3 DDR3 VDDQ Line Regulation .................................................................................. 10

7.4 DDR3 VTT Load Regulation .................................................................................... 11

7.5 DDR3 VTTREF Load Regulation ............................................................................... 11

7.6 DDR3 VTT Dropout Voltage .................................................................................... 12

7.7 DDR3 S5 Enable Turnon/Turnoff ............................................................................... 12

7.8 S5 Enable Turnon with 1-V Prebias at VDDQ ................................................................ 13

7.9 DDR3 S3 Enable Turnon/ Turnoff (S5 is ON) ................................................................ 13

7.10 DDR3 VDDQ Output Ripple ..................................................................................... 14

7.11 DDR3 VDDQ Switching Node .................................................................................. 14

7.12 DDR3 VDDQ Output Transient ................................................................................. 15

7.13 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current ........................................... 15

7.14 Thermal Image .................................................................................................... 16

7.15 DDR3 VDDQ Bode Plot ......................................................................................... 16

7.16 DDR3 VTT Bode Plot ............................................................................................ 17

8 EVM Assembly Drawing and PCB Layout ............................................................................. 17

9 Bill of Materials ............................................................................................................. 21

List of Figures

D-CAP2 is a trademark of Texas Instruments.

SLUU526–August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4

Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered

Submit Documentation Feedback

Reference

www.ti.com

1 TPS51916EVM-746 Schematic ........................................................................................... 5

2 Tip and Barrel Measurement for VDDQ Output Ripple ................................................................ 6

3 TPS51916EVM-746 Recommended Test Setup ....................................................................... 7

4 DDR3 VDDQ Efficiency .................................................................................................... 9

5 DDR3 VDDQ Load Regulation .......................................................................................... 10

6 DDR3 VDDQ Line Regulation ........................................................................................... 10

7 DDR3 VTT Load Regulation ............................................................................................. 11

8 DDR3 VTTREF Load Regulation........................................................................................ 11

9 DDR3 VTT Dropout Voltage ............................................................................................. 12

10 DDR3 S5 Enable Turnon ................................................................................................. 12

11 DDR3 S5 Enable Turnoff ................................................................................................. 12

12 DDR3 S5 Enable Turnon With 1-V Prebias at VDDQ ................................................................ 13

13 DDR3 S3 Enable Turnon ................................................................................................. 13

14 DDR3 S3 Enable Turnoff ................................................................................................. 13

15 DDR3 VDDQ Output Ripple ............................................................................................. 14

16 DDR3 VDDQ Switching Node ........................................................................................... 14

17 VDDQ Output Transient From DCM to CCM ......................................................................... 15

18 VDDQ Output Transient From CCM to DCM ......................................................................... 15

19 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current.................................................... 15

20 Top Board at 12 Vin, 1.5 VDDQ/20 A, No Load at VTT, 25°C Ambient Without Airflow ........................ 16

21 DDR3 VDDQ Bode Plot at 12 Vin, 1.5 VDDQ/10 A................................................................... 16

22 DDR3 VTT Bode Plot at 12 Vin, 1.5 VDDQ/0 A and VTT 1-A Sourcing ........................................... 17

23 TPS51916EVM-746 Top Layer Assembly Drawing................................................................... 17

24 TPS51916EVM-746 Bottom Assembly Drawing ...................................................................... 18

25 TPS51916EVM-746 Top Copper ....................................................................................... 18

26 TPS51916EVM-746 Layer-2 Copper ................................................................................... 19

27 TPS51916EVM-746 Layer-3 Copper ................................................................................... 19

28 TPS51916EVM-746 Bottom Copper ................................................................................... 20

List of Tables

1 TPS51916EVM-746 Electrical Performance Specifications ........................................................... 3

2 S3, S5 Enable Selection ................................................................................................... 8

3 Test Point Functions........................................................................................................ 8

4 TPS51916EVM-746 Bill of Materials.................................................................................... 21

Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526– August 2011

Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered

Submit Documentation Feedback

Reference

www.ti.com

Description

1 Description

The TPS51916EVM-746 is designed to use a regulated 12-V bus to produce a regulated 1.5-VDDQ output

at up to a 20-A load current. The TPS51916EVM-746 demonstrates TPS51916 in a typical DDR3

application with D-CAP2™-mode operation. The EVM also provides test points to evaluate the

performance of the TPS51916.

1.1 Typical Applications

• DDR2/DDR2/DDR3L/DDR4 memory power supplies

• SSTL_18, SSTL_15, SSTL_135, and HSTL termination

1.2 Features

The TPS51916EVM-746 features:

• D-CAP2™-mode operation with all-ceramic VDDQ output capacitor

• 20-Adc steady-state VDDQ output current

• Support VDDQ prebias start-up

• SW1 and SW2 provides S3, S5 power control

• Optional external VLDOIN voltage for efficiency and flexible operation

• Convenient test points for probing critical waveforms

2 Electrical Performance Specifications

Table 1. TPS51916EVM-746 Electrical Performance Specifications

Parameter Test Conditions Min Typ Max Units

Input Characteristics

Voltage range VIN 8 12 20 V

V5IN 4.5 5 5.5

Maximum input current VIN = 8 V, I

VDDQ

= 20 A 4.21 A

No-load input current Vin = 20 V, I

VDDQ

= 0 A 0.1 mA

VDDQ Output

DDR3 (Default setting), R15 = 47.5k, R16 = 2k 1.5 V

DDR2, R15 = R16= Open 1.8 V

VDDQ Output voltage

(VDDQSNS)

DDR3L, R15 = 28k, R16 = 2k 1.35 V

DDR4, R15 = 18.2k, R16 = 2k 1.2 V

VDDQ Output voltage regulation Line regulation (Vin = 8 V–20 V) 0.2%

Load regulation (Vin = 12 V, I

VDDQ

= 0 A–20 A) 0.5%

Output voltage ripple Vin = 12 V, I

VDDQ

= 20 A 20 mVpp

Output load current 0 20 A

Output overcurrent 30 A

Switching frequency 500 kHz

Peak efficiency Vin = 12 V, 1.5 VDDQ/8 A 90.93%

Full-load efficiency Vin = 12 V, 1.5 VDDQ/20 A 87.3%

VTT Output

VTT output voltage VTTREF V

For DDR2(0.9 VTT) and DDR3(0.75 VTT) –2 2 A

VTT output current

For DDR3L(0.675 VTT) and DDR4(0.6 VTT) –1.5 1.5 A

VTT

| < 2 A, 1.4 V ≤ V

VDDQSNS

≤ 1.8 V –40 40 mV

VTT output tolerance to VTTREF

VTT

| < 1.5 A, 1.2 V ≤ V

VDDQSNS

< 1.4 V –40 40 mV

VTTREF Output

VTTREF output voltage VDDQSNS/2 V

VTTREF output current –10 10 mA

SLUU526–August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4

Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered

Submit Documentation Feedback

Reference

Part #	GRM32ER60J107ME20L
Description	CAP 100UF 6.3VDC X5R 20% SMD1210 - Cut TR (SOS) Additional Information:
Category	CAPACITOR
Availability	Out of Stock
Qty	0

GRM32ER60J107ME20L

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