5
2. V
Logic
ECL Contact Pad
Under normal conditions
no connection or external bias
is required to this pad and it
is self-biased to the on-chip ECL
logic threshold voltage
(V
CC
-1.35 V). The user can
provide an external bias to this pad
(1.5 to 1.2 volts less than V
CC
) to force
the prescaler to
operate at a system generated logic
threshold voltage.
3. Input Disable Feature
If an RF signal with suffi cient signal-
to-noise ratio is present at the RF
input, the prescaler will operate and
provide a divided output equal to the
input frequency divided by the divide
modulus. Under certain “ideal” condi-
tions where the input is well matched
at the right input frequency, the
device may “self-oscillate,” especially
under small signal input powers or
with only noise present at the input.
This “self-oscillation” will produce a
undesired output signal also known
as a false trigger. By applying an
external bias to the input disable
contact pad (more positive than V
CC
-
1.35 V), the input preamplifi er stage is
locked into either logic “high” or logic
“low” preventing frequency division
and any self-oscillation frequency
which may be present.
4. Input dc Offset
Another method used to prevent false
triggers or self-oscillation
conditions is to apply a 20 to
100 mV dc offset voltage between
the RF
in
and RF
in
ports. This prevents
noise or spurious low level signals
from triggering the divider.
Adding a 10 K resistor between the
unused RF input to a contact point at
the V
EE
potential will result in an off-
set of ≈25 mV between the RF inputs.
Note however, that the input sensitivity
will be reduced slightly due to the
presence of this offset.
Assembly Techniques
Figure 3 shows the chip assembly
diagram for single-ended I/O opera-
tion through 12 GHz for either positive
or negative bias supply operation. In
either case the supply contact to the
chip must be capacitively bypassed to
provide good input sensitivity and low
input power feedthrough. Independent
of the bias applied to the device, the
backside of the chip should always be
connected to both a good RF ground
plane and a good thermal heat sinking
region on the mounting surface.
All RF ports are dc connected
on-chip to the V
CC
contact through
on-chip 50 resistors. Under any
bias conditions where V
CC
is not dc
grounded, the RF ports should be ac
coupled via series capacitors mounted
on the thin-fi lm substrate at each RF
port. Only under bias conditions where
V
CC
is dc grounded (as is typical for
negative bias supply operation) may
the RF ports be direct coupled to adja-
cent circuitry or in some cases, such
as level shifting to subsequent stages.
In the latter case the device backside
may be “fl oated” and bias applied as
the difference between V
CC
and V
EE
.
All bonds between the device and this
bypass capacitor should be as short
as possible to limit the inductance.
For operation at frequencies below 1
GHz, a large value capacitor must be
added to provide proper RF bypassing.
Due to on-chip 50 matching resis-
tors at all four RF ports, no external
termination is required on any unused
RF port. However, improved “Spit-
back” performance (
~
20 dB) and
input sensitivity can be achieved by
terminating the unused RF
out
port to
V
CC
through 50 (positive supply) or
to ground via
a 50 termination (negative
supply operation).
GaAs MMICs are ESD sensitive.
ESD preventive measures must be
employed in all aspects of storage,
handling, and assembly.
MMIC ESD precautions, handling
considerations, die attach and bond-
ing methods are critical factors in suc-
cessful GaAs MMIC performance and
reliability.
Agilent application note #54, “GaAs
MMIC ESD, Die Attach and Bonding
Guidelines” provides basic
information on these subjects.
