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ADP3338AKCZ-3.3RL7

Part # ADP3338AKCZ-3.3RL7
Description LDO Regulator Pos 3.3V 1.6A 4-Pin(3+Tab) SOT-223 T/R - Tap
Category VOLTAGE REGULAT
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Analog Devices
Date Code: 1222
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ADP3338
Rev. B | Page 10 of 16
APPLICATION INFORMATION
CAPACITOR SELECTION
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3338 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as
low as 1 µF is the only requirement for stability. A higher ca-
pacitance may be necessary if high output current surges are
anticipated, or if the output capacitor cannot be located near the
output and ground pins. The ADP3338 is stable with extremely
low ESR capacitors (ESR ≈ 0) such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types falls below the minimum over temperature or
with dc voltage.
Input Capacitor
An input bypass capacitor is not strictly required, but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1 µF capacitor from the input
to ground reduces the sensitivity of the circuit to PC board
layout and input transients. If a larger output capacitor is
necessary, a larger value input capacitor is recommended.
OUTPUT CURRENT LIMIT
The ADP3338 is short-circuit protected by limiting the pass
transistors base drive current. The maximum output current is
limited to approximately 2 A (see Figure 16).
THERMAL OVERLOAD PROTECTION
The ADP3338 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit.
Thermal protection limits the die temperature to a maximum of
160°C. Under extreme conditions, such as high ambient
temperature and power dissipation where the die temperature
starts to rise above 160°C, the output current is reduced until
the die temperature has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, externally limit the power dissipation of the device
so the junction temperature does not exceed 150°C.
CALCULATING POWER DISSIPATION
Device power dissipation is calculated as
P
D
= (V
IN
V
OUT
) × I
LOAD
+ (V
IN
× I
GND
)
Where I
LOAD
and I
GND
are load current and ground current, and
V
IN
and V
OUT
are the input and output voltages, respectively.
Assuming the worst-case operating conditions are I
LOAD
= 1.0 A,
I
GND
= 10 mA, V
IN
= 3.3 V, and V
OUT
= 2.5 V, the device power
dissipation is
P
D
= (3.3 V – 2.5 V) × 1000 mA + (3.3 V × 10 mA) = 833 mW
So, for a junction temperature of 125°C and a maximum
ambient temperature of 85°C, the required thermal resistance
from junction to ambient is
C/W48
W833.0
C85C125
°=
°°
=θ
JA
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The thermal resistance, θ
JA
, of the SOT-223 is determined by the
sum of the junction-to-case and the case-to-ambient thermal
resistances. The junction-to-case thermal resistance, θ
JC
, is
determined by the package design and is specified at 26.8°C/W.
However, the case-to-ambient thermal resistance is determined
by the printed circuit board design.
As shown in Figure 22, the amount of copper to which the
ADP3338 is mounted affects thermal performance. When
mounted to the minimal pads of 2 oz. copper, as shown in
Figure 22 (a), θ
JA
is 126.6°C/W. Adding a small copper pad
under the ADP3338, as shown in Figure 22 (b), reduces the θ
JA
to
102.9°C/W. Increasing the copper pad to one square inch, as
shown in Figure 22 (c), reduces the θ
JA
even further to 52.8°C/W.
02050-022
cab
Figure 22. PCB Layouts
ADP3338
Rev. B | Page 11 of 16
Use the following general guidelines when designing printed
circuit boards:
Keep the output capacitor as close as possible to the output
and ground pins.
Keep the input capacitor as close as possible to the input
and ground pins.
Specify thick copper and use wide traces for optimum heat
transfer. PC board traces with larger cross sectional areas
remove more heat from the ADP3338.
Decrease thermal resistance by adding a copper pad under
the ADP3338, as shown in Figure 22 (b).
Use the adjacent area to the ADP3338 to add more copper
around it. Connecting the copper area to the output of the
ADP3338, as shown in Figure 22 (c), is best, but thermal
performance will be improved even if it is connected to
other signals.
Use additional copper layers or planes to reduce the
thermal resistance. Again, connecting the other layers to
the output of the ADP3338 is best, but is not necessary.
When connecting the output pad to other layers, use
multiple vias.
ADP3338
Rev. B | Page 12 of 16
OUTLINE DIMENSIONS
SEATING
PLANE
4.60 BSC
10° MAX
16°
10°
16°
10°
321
2.30
BSC
0.84
0.76
0.66
6.50 BSC
1.70
1.60
1.50
1.05
0.85
0.10
0.02
1.30
1.10
0.35
0.30
0.23
3.10
3.00
2.90
3.70
3.50
3.30
7.30
7.00
6.70
COMPLIANT TO JEDEC STANDARDS TO-261-AA
Figure 23. 3-Lead Small Outline Transistor Package [SOT-223]
(KC-3)
Dimensions shown in millimeters
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