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ADP3338AKCZ-3.3RL7

Part # ADP3338AKCZ-3.3RL7
Description LDO Regulator Pos 3.3V 1.6A 4-Pin(3+Tab) SOT-223 T/R - Tap
Category VOLTAGE REGULAT
Availability In Stock
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Qty Price
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Analog Devices
Date Code: 1222
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ADP3338
Rev. B | Page 7 of 16
LOAD CURRENT (A)
DROPOUT (mV)
250
200
0
0 0.2 1.0
0.4 0.6 0.8
150
100
50
V
OUT
= 2.5V
02050-010
Figure 10. Dropout Voltage vs. Load Current
0 56789
TIME (sec)
V
OUT
= 2.5V
I
LOAD
= 1A
INPUT/OUTPUT VOLTAGE (V)
0
1
2
3
02050-011
1
2
3
4
10
Figure 11. Power-Up/Power-Down
3.5
8040
TIME (µs)
V
OUT
= 2.5V
C
OUT
= 1µF
I
LOAD
= 1A
120 160 200 240
4.5
2.50
2.49
2.51
VOLTS
02050-012
Figure 12. Line Transient Response
3.5
8040
TIME (
µ
s)
V
OUT
= 2.5V
C
OUT
= 10µF
I
LOAD = 1A
120 160 200 240
4.5
2.50
2.49
2.51
VOLTS
02050-013
Figure 13. Line Transient Response
0
2000
TIME (
µ
s)
400 600 800 1000
1
2.5
2.4
2.6
VOLTS
02050-014
A
V
IN
= 6V
C
OUT
= 1
µ
F
Figure 14. Load Transient Response
0
2000
TIME (
µ
s)
400 600 800 1000
1
2.5
2.4
2.6
VOLTS
02050-015
A
V
IN
= 6V
C
OUT
= 10
µ
F
Figure 15. Load Transient Response
ADP3338
Rev. B | Page 8 of 16
V
IN
= 6V
400m
SHORT
FULL SHORT
0
0.4
TIME (s)
0.6 0.8 1.0
0.5
0
2.5
VOLTS
02050-016
A
1.0
1.5
Figure 16. Short-Circuit Current
FREQUENCY (Hz)
10
100 1k 10k 100k 1M
V
OUT
= 2.5V
C
L
= 10
µ
F
I
L
= 1A
–80
–70
–60
–50
–40
–30
–20
–10
–90
–100
0
RIPPLE REJECTION (dB)
02050-017
C
L
= 1
µ
F
I
L
= 1A
C
L
= 10
µ
F
I
L
= 0
C
L
= 1
µ
F
I
L
= 0
Figure 17. Power Supply Ripple Rejection
C
L
(
µ
F)
RMS NOISE (
µ
V)
250
200
0
010
5020 30 40
150
100
50
300
I
L
= 1A
I
L
= 0A
02050-018
Figure 18. RMS Noise vs. C
L
FREQUENCY (Hz)
10 100
1k
10k
100k
1M
C
L
= 1µF
0.001
0.01
0.1
1
10
100
C
L
= 10µF
VOLTAGE NOISE SPECTRAL DENSITY (µV/Hz)
02050-019
Figure 19. Output Noise Density (10 Hz to 100 kHz)
ADP3338
Rev. B | Page 9 of 16
THEORY OF OPERATION
The ADP3338 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider, consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium produces
a large, temperature-proportional input offset voltage that is
repeatable and very well controlled. The temperature-propor-
tional offset voltage is combined with the complementary diode
voltage to form a virtual band gap voltage that is implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexi-
bility on the trade off of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by Diode D1 and a second divider consisting
of R3 and R4, the values can be chosen to produce a tempera-
ture-stable output. This unique arrangement specifically corrects
for the loading of the divider, thus avoiding the error resulting
from base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value required to keep conventional
LDOs stable changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
With the ADP3338 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no
constraint on the minimum ESR. This innovative design
provides circuit stability with just a small 1 µF capacitor on the
output. Additional advantages of the pole-splitting scheme
include superior line noise rejection and very high regulator
gain to achieve excellent line and load regulation. An impressive
±1.4% accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and
thermal shutdown.
V
IN
OUT
ADP3338
C1
1
µ
F
C2
1
µ
F
V
OUT
GNDIN
02050-021
Figure 20. Typical Application Circuit
PTAT
V
OS
g
m
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3338
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGAP
/V
OUT
)
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
GND
C
LOAD
R
LOAD
02050-020
Figure 21. Functional Block Diagram
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