Digital Interface

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All of the pins on J4 and J8 are connected with minimal filtering or protection. Use appropriate caution

when handling these pins. Table 1 summarizes the pinouts for analog interfaces J4 and J8.

Table 1. J8/J4: Analog Interface Pinout

Pin Number Signal Description, ADS1148/ADS1248

J8.1, J4-1 A0(–) AIN0

J8.2, J4-2 A0(+) AIN1

J8.3, J4-3 A1(–) AIN2

J8.4, J4-4 A1(+) AIN3

J8.5, J4-5 A2(–) AIN4

J8.6, J4-6 A2(+) AIN5

J8.7, J4-7 A3(–) AIN6

J8.8, J4-8 A3(+) AIN7

J8.18 REF– External reference source input (–

side of differential input)

J8.20 REF+ External reference source input (+

side of differential input)

J8.10-16 (even) Unused

J8.15 Unused

J8.9-19 (odd), J4-9 AGND Analog ground connections

(except J8.15)

3 Digital Interface

3.1 Serial Data Interface

The ADS1248EVM is designed to easily interface with multiple control platforms. Samtec part numbers

SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket

combination at J7. This header/socket provides access to the digital control and serial data pins of the

ADC. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating

connector options.

All logic levels on J7 are 3.3V CMOS, except for the I

C™ pins. These pins conform to 3.3V I

C rules.

Table 2 describes the J7 serial interface pins.

Table 2. J7: Serial Interface Pins

Pin No. Pin Name Signal Name I/O Type Pullup Function

J7.1 CNTL CS In High

J7.2 GPIO0 START In High

J7.3 CLKX SCLK In None ADS1248 SPI clock

J7.4 DGND DGND In/Out None Digital ground

J7.5 CLKR Unused – –

J7.6 GPIO1 MR In High Master reset

J7.7 FSX Unused – –

J7.8 GPIO2 Unused – –

J7.9 FSR DRDY Out None

J7.10 DGND DGND In/Out None Digital ground

J7.11 DX DIN In None ADS1248 SPI data in

J7.12 GPIO3 PWRSEL In High Selects ±2.5V or +5V

supply

J7.13 DR DOUT/DRDY Out None ADS1248 data out

J7.14 GPIO4 Unused – –

J7.15 INT DRDY Out None

ADS1148EVM, ADS1248EVM, ADS1148EVM-PDK, and ADS1248EVM-PDK SBAU142B– April 2009–Revised May 2011

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Power Supplies

Table 2. J7: Serial Interface Pins (continued)

Pin No. Pin Name Signal Name I/O Type Pullup Function

J7.16 SCL SCL I

C High I

C clock

J7.17 TOUT CLK In None Can be used to provide

a clock from a

processor

J7.18 DGND DGND In/Out None Digital ground

J7.19 GPIO5 CLK Select – None

J7.20 SDA SDA I

C High I

C data

Many pins on J7 have weak pull-up resistors. These resistors provide default settings for many of the

control pins. Many pins on J7 correspond directly to ADS1248 pins. See the ADS1248 product data sheet

for complete details on these pins.

4 Power Supplies

J11 is the power-supply input connector. Table 3 lists the configuration details for J11.

Table 3. J11 Configuration: Power-Supply Input

Pin No. Pin Name Function Required

J11.1 +VA Unused No

J11.2 –VA Unused No

J11.3 +5VA +5V analog supply Always

J11.4 –5VA –5V analog supply Only in bipolar mode

J11.5 DGND Digital ground input Yes

J11.6 AGND Analog ground input Yes

J11.7 +1.8VD 1.8V digital supply No

J11.8 VD1 Unused No

J11.9 +3.3VD 3.3V digital supply Always

J11.10 +5VD +5V digital supply No

All of the power supplies (AVDD, AVSS, and DVDD) have corresponding jumpers on J10 that can be

replaced with a current meter to measure the respective supply currents.

4.1 Power Options

J10 is arranged as five rows, each of which can be shorted. Table 4 lists the power option details for J10.

For normal operation, J10.1-2, J10.3-4, and J10.5-6 must be connected (direct or through an ammeter),

and either (or both) of J10.7-8 and J10.9-10 must be connected; otherwise, the board does not function.

Table 4. J10 Configuration: Power Options

Row Name Function

1-2 ADC AVDD AVDD supply current measurement point for the ADC. Must be

connected for operation.

3-4 ADC AVSS AVSS supply current measurement point for the ADC. Must be

connected for operation.

5-6 ADC DVDD DVDD supply current measurement point for the ADC. Must be

connected for operation.

7-8 DGND Connects DGND to board ground.

9-10 AGND Connects AGND to board ground.

SBAU142B– April 2009–Revised May 2011 ADS1148EVM, ADS1248EVM, ADS1148EVM-PDK, and ADS1248EVM-PDK

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Voltage Reference

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5 Voltage Reference

The ADS1248 device has the option of selecting between three different references: REF0, REF1, and the

internal reference, through registers in the ADS1248 chip. The EVM provides a 2.048V reference for

REF1 from U1, filtered and buffered through U2. This 2.048V may be used to drive the REF1P input.

REF1P should not be connected to AVDD through switch S1 because this connection will violate the

specification for the maximum reference input. Figure 1 shows switch S1 as it appears on the EVM. The

low side of the reference (REF1N) is tied to AVSS.The different reference options under different supply

conditions are outlined in Table 5.

Figure 1. Reference Select Switch S1

Table 5. REF1 Reference Voltage Options

REF1

S1 Position Reference

AVDD AVSS J1 Setting

(1)

REF1P REF1N Voltage

5V 0V 1-2 BUFF 2.048V 0V 2.048V

5V 0V 2-3 BUFF 0V 0V Invalid

selection

2.5V –2.5V 1-2 BUFF –0.452V –2.5V 2.048V

2.5V –2.5V 2-3 BUFF 0V –2.5V 2.5V

(1)

Switch S1 should not be set to AVDD.

The REF0N and REF0P pins are connected directly to the external reference pins on J8.18 and J8.20,

respectively. These pins are diode-clamped to AVDD and AVSS, and protected with D3, a 5.1V zener. If

the external reference pins are not supplied with a external source, REF0N will be at approximately AVSS

+ 0.6V, and REF0P will be at approximately AVDD–0.6V.

The internal reference voltage can be measured between testpoints TP3 (Int REF) and TP5 (REFCOM).

6 Clock Source

The ADS1248 has an internal clock or can be provided an external clock. The EVM uses the internal clock

mode only. Provision is made on the EVM circuit board, however, for an external clock source. A footprint

is provided at U8 for a crystal oscillator to be mounted on the board. An external clock may also be

provided by a processor on the TOUT pin (J7.17), or an external clock source connected to J14.1 (ground)

and J14.2 (signal).

J2 controls how the clock source is selected. With pins J2.1 and J2.2 shorted, GPIO5 from J7.19 can

control whether the A or B side of U7 is selected. If the A side is selected, the clock should come from an

external source provided as described above. If the B side is selected, the clock should come from the

crystal oscillator. If a selection is made and no clock is provided on that input, the ADS1248 detects that

no external clock is present and enables its internal oscillator.

6.1 Usage in PDK

If using the ADS1248EVM as part of the ADS1248EVM-PDK, J14 should have a jumper installed.

Remove any shorting blocks on jumper J13, and make sure J2 has a jumper between pins 1 and 2 (the IO

position). This configuration grounds the CLK input to the ADS1248 and ensures that the internal oscillator

starts up.

ADS1148EVM, ADS1248EVM, ADS1148EVM-PDK, and ADS1248EVM-PDK SBAU142B– April 2009–Revised May 2011

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Part #	ERJ-3EKF2001V
Description	RES THKFLM 0603 2K OHM 1% 1/10W 100PPM/ C SMD - Cut TR (SO
Category	RESISTOR
Availability	Out of Stock
Qty	0

ERJ-3EKF2001V

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