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MC74VHC1GT08DFT2

Part # MC74VHC1GT08DFT2
Description Logic Gates 3-5.5V Single AND
Category RECTIFIER
Availability In Stock
Qty 1000
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211 - 420 $0.04565
421 - 630 $0.04305
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ON Semiconductor
Date Code: 03
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 5
1 Publication Order Number:
MC74VHC1GT08/D
MC74VHC1GT08
2-Input AND Gate/CMOS
Logic Level Shifter
The MC74VHC1GT08 is an advanced high speed CMOS 2–input AND
gate fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input, allowing
the device to be used as a logic–level translator from 3.0 V CMOS logic to
5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic
while operating at the high–voltage power supply.
The MC74VHC1GT08 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT08 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when V
CC
= 0 V.
These input and output structures help prevent device destruction caused
by supply voltage input/output voltage mismatch, battery backup, hot
insertion, etc.
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1 µA (Max) at T
A
= 25°C
TTL–Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
CMOS–Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 64; Equivalent Gates = 15
V
CC
IN B
IN A
OUT YGND
IN A
IN B
OUT Y
&
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
1
2
34
5
PIN ASSIGNMENT
1
2
3 GND
IN B
IN A
4
5V
CC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
L
L
H
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
SC–88A / SOT–353/SC–70
DF SUFFIX
CASE 419A
Pin 1
d = Date Code
VT
d
TSOP–5/SOT–23/SC–59
DT SUFFIX
CASE 483
Pin 1
d = Date Code
VT
d
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MC74VHC1GT08
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2
MAXIMUM RATINGS (Note 1)
Symbol
Characteristics Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
IN
DC Input Voltage –0.5 to +7.0 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current –20 mA
I
OK
Output Diode Current V
OUT
< GND; V
OUT
> V
CC
+20 mA
I
OUT
DC Output Current, per Pin +25 mA
I
CC
DC Supply Current, V
CC
and GND +50 mA
P
D
Power dissipation in still air SC–88A, TSOP–5 200 mW
JA
Thermal resistance SC–88A, TSOP–5 333 C/W
T
L
Lead temperature, 1 mm from case for 10 s 260 °C
T
J
Junction temperature under bias +150 °C
T
stg
Storage temperature –65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
I
Latch–Up
Latch–Up Performance Above V
CC
and Below GND at 125°C (Note 5) ±500 mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 3.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
0.0
0.0
5.5
V
CC
V
T
A
Operating Temperature Range –55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ± 0.3 V
V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 80
C°
T
J
= 90
C°
T
J
= 100 C°
T
J
= 110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time
Junction Temperature
MC74VHC1GT08
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3
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= 25°C T
A
85°C –55 T
A
125°C
Symbol Parameter Test Conditions
V
CC
(V)
Min Typ Max Min Max Min Max
Unit
V
IH
Minimum High–Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low–Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High–Level
Output Voltage
VV V
V
IN
= V
IH
or V
IL
I
OH
= –50 µA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
g
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= –4 mA
I
OH
= –8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OL
Maximum Low–Level
Output Voltage
VV V
V
IN
= V
IH
or V
IL
I
OL
= 50 µA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
g
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
I
IN
Maximum Input
Leakage Current
V
IN
= 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0 µA
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 1.0 20 40 µA
I
CCT
Quiescent Supply
Current
Input: V
IN
= 3.4 V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage
Current
V
OUT
= 5.5 V 0.0 0.5 5.0 10 µA
AC ELECTRICAL CHARACTERISTICS C
load
= 50 pF, Input t
r
= t
f
= 3.0 ns
T
A
= 25°C T
A
85°C –55 T
A
125°C
Symbol Parameter Test Conditions
Min Typ Max Min Max Min Max
Unit
t
PLH
,
t
PHL
Maximum
Propagation Delay,
ItABtY
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
4.1
5.9
8.8
12.3
10.5
14.0
12.5
16.5
ns
PHL
gy
Input A or B to Y
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
3.5
4.2
5.9
7.9
7.0
9.0
9.0
11.0
C
IN
Maximum Input
Capacitance
5.5 10 10 10 pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Note 6)
11
pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no–load dynamic
power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
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