1
Data sheet acquired from Harris Semiconductor
SCHS188C
Features
• Buffered Inputs
• Common Three-State Output-Enable Control
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay = 13ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C (Clock to Output)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed
Octal D-Type Flip-Flops manufactured with silicon gate CMOS
technology. They possess the low power consumption of stan-
dard CMOS integrated circuits, as well as the ability to drive
15 LSTTL loads. Due to the large output drive capability and
the three-state feature, these devices are ideally suited for
interfacing with bus lines in a bus organized system. The two
types are functionally identical and differ only in their pinout
arrangements.
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive
edge triggered flip-flops. Data at the D inputs, meeting the
setup and hold time requirements, are inverted and trans-
ferred to the Q outputs on the positive going transition of the
CLOCK input. When a high logic level is applied to the OUT-
PUT ENABLE input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs and
the state of the storage elements.
The HCT logic family is speed, function, and pin compatible
with the standard LS logic family.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC534F3A -55 to 125 20 Ld CERDIP
CD54HC564F3A -55 to 125 20 Ld CERDIP
CD54HCT534F3A -55 to 125 20 Ld CERDIP
CD54HCT564F3A -55 to 125 20 Ld CERDIP
CD74HC534E -55 to 125 20 Ld PDIP
CD74HC564E -55 to 125 20 Ld PDIP
CD74HC564M -55 to 125 20 Ld SOIC
CD74HC564M96 -55 to 125 20 Ld SOIC
CD74HCT534E -55 to 125 20 Ld PDIP
CD74HCT564E -55 to 125 20 Ld PDIP
CD74HCT564M -55 to 125 20 Ld SOIC
January 1998 - Revised April 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
CD54/74HC534, CD54/74HCT534,
CD54/74HC564, CD54/74HCT564
High-Speed CMOS Logic Octal D-Type Flip-Flop,
Three-State Inverting Positive-Edge Triggered
[ /Title
(CD74
HC534
,
C
D74
HCT53
4,
CD74
HC564
,
C
D74
HCT56
