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CD54HC251F

Part # CD54HC251F
Description 8-INPUT MULTIPLEXER - Rail/Tube
Category Microcircuit
Availability In Stock
Qty 4
Qty Price
1 - 2 $14.20151
3 + $10.75872
Manufacturer Available Qty
Harris Corporation
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Data sheet acquired from Harris Semiconductor
SCHS169C
Features
Selects One of Eight Binary Data Inputs
Three-State Output Capability
True and Complement Outputs
Typical (Data to Output) Propagation Delay of 14ns at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
Alternate Source is Philips
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1µA at V
OL
, V
OH
Pinout
CD54HC251, CD54HCT251
(CERDIP)
CD74HC251, CD74HCT251
(PDIP, SOIC)
TOP VIEW
Description
The ’HC251 and ’HCT251 are 8-channel digital multiplexers
with three-state outputs, fabricated with high-speed silicon-
gate CMOS technology. Together with the low power
consumption of standard CMOS integrated circuits, they
possess the ability to drive 10 LSTTL loads. The three-state
feature makes them ideally suited for interfacing with bus
lines in a bus-oriented system.
This multiplexer features both true (Y) and complement (
Y)
outputs as well as an output enable (
OE) input. The OE must
be at a low logic level to enable this device. When the
OE
input is high, both outputs are in the high-impedance state.
When enabled, address information on the data select inputs
determines which data input is routed to the Y and
Y
outputs. The ’HCT251 logic family is speed, function, and
pin-compatible with the standard ’LS251.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
I
3
I
2
I
1
I
0
Y
Y
GND
OE
V
CC
I
5
I
6
I
7
S0
S1
S2
I
4
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC251F3A -55 to 125 16 Ld CERDIP
CD54HCT251F3A -55 to 125 16 Ld CERDIP
CD74HC251E -55 to 125 16 Ld PDIP
CD74HC251M -55 to 125 16 Ld SOIC
CD74HC251MT -55 to 125 16 Ld SOIC
CD74HC251M96 -55 to 125 16 Ld SOIC
CD74HCT251E -55 to 125 16 Ld PDIP
CD74HCT251M -55 to 125 16 Ld SOIC
CD74HCT251MT -55 to 125 16 Ld SOIC
CD74HCT251M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC251, CD74HC251,
CD54HCT251, CD74HCT251
High-Speed CMOS Logic
8-Input Multiplexer, Three-State
[
/Title
(
CD74
H
C251
,
C
D74
H
CT25
1
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
8
-Input
M
ulti-
p
lexer;
T
hree-
2
Functional Diagram
TRUTH TABLE
INPUTS OUTPUT
SELECT
OUTPUT
CONTROL OE Y YS2 S1 S0
XXX H ZZ
LLL L I
0
I
0
LLH L I
1
I
1
LHL L I
2
I
2
LHH L I
3
I
3
HLL L I
4
I
4
HLH L I
5
I
5
HHL L I
6
I
6
HHH L I
7
I
7
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance
(Off), I
0
, I
1
...I
7
= the level of the respective input.
5
6
Y
Y
4
3
2
1
14
12
13
15
I
0
I
7
I
6
I
5
I
4
I
3
I
2
I
1
11
S
0
10
S
1
9
S
2
7
OE
CHANNEL
INPUTS
DATA
SELECT
OUTPUTS
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
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