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SNJ54ALS138AW

Part # SNJ54ALS138AW
Description Decoder/Demultiplexer Single3-to-8 16-Pin CFPAK Tube - Ra
Category IC
Availability In Stock
Qty 21
Qty Price
1 - 4 $28.36629
5 - 8 $22.56409
9 - 13 $21.27471
14 - 17 $19.77044
18 + $17.62148
Manufacturer Available Qty
Texas Instruments
Date Code: 9812
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JULY 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ALS138A and AS138 are 3-line to 8-line
decoders/demultiplexers designed for high-
performance memory-decoding or data-routing
applications requiring very short propagation
delay times. In high-performance systems, these
devices can be used to minimize the effects of
system decoding. When employed with
high-speed memories with a fast enable circuit,
the delay times of the decoder and the enable time
of the memory are usually less than the typical
access time of the memory. The effective system
delay introduced by the Schottky-clamped system
decoder is negligible.
The conditions at the binary-select (A, B, and C)
inputs and the three enable (G1, G2A
, and G2B)
inputs select one of eight output lines. Two
active-low and one active-high enable inputs
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input
for demultiplexing applications.
The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS138A, SN54AS138 ...J PACKAGE
SN74ALS138A, SN74AS138 ...D OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
SN54ALS138A, SN54AS138 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
Y6
Y5
Y0
Y7
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JULY 1996
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE SELECT
OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HLLHHHHHHHHHHL
logic symbols (alternatives)
BIN/OCT
1
1
A
2
2
B
4
3
C
4
5
6
G1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
DMUX
0
1
A
2
B
2
3
C
4
5
6
G1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
G
7
0
G2A
G2B
G2A
G2B
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JULY 1996
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
G2B
G2A
G1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
6
4
5
15
14
13
12
11
10
9
7
Pin numbers shown are for the D, J, and N packages.
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