Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

TLV2472CD

Part # TLV2472CD
Description DUAL OPAMP LOW POWER RAIL TORAIL I/O - Rail/Tube
Category IC
Availability In Stock
Qty 75
Qty Price
1 - 15 $1.35464
16 - 31 $1.07755
32 - 47 $1.01598
48 - 63 $0.94414
64 + $0.84152
Manufacturer Available Qty
Texas Instruments
  • Shipping Freelance Stock: 1
    Ships Immediately
Texas Instruments
  • Shipping Freelance Stock: 74
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA
FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT
HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS232C - JUNE 1999 - REVISED AUGUST 2003
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 47. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils
in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θ
JA
, the maximum power dissipation is shown in Figure 48 and is calculated by the following formula:
P
D
+
ǒ
T
MAX
T
A
q
JA
Ǔ
Where:
P
D
= Maximum power dissipation of TLV247x IC (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
T
A
= Free-ambient air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θ
JC
= Thermal coefficient from junction to case
θ
CA
= Thermal coefficient from case to ambient air (°C/W)
TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA
FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT
HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS232C - JUNE 1999 - REVISED AUGUST 2003
20
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
T
J
= 150°C
4
3
2
0
-55 -40 -10 20 35
Maximum Power Dissipation - W
5
6
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
65 95 125
1
T
A
- Free-Air Temperature - °C
DGN Package
Low-K Test PCB
θ
JA
= 52.3°C/W
SOT-23 Package
Low-K Test PCB
θ
JA
= 324°C/W
-25 5 50 80 110
PWP Package
Low-K Test PCB
θ
JA
= 29.7°C/W
SOIC Package
Low-K Test PCB
θ
JA
= 176°C/W
PDIP Package
Low-K Test PCB
θ
JA
= 104°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 48. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 49 to Figure 54 show this effect,
along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using V
DD
= 3 V, there
is generally not a heat problem with an ambient air temperature of 70°C. But, when using V
DD
= 5 V, the
packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these
graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation
properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted
on the PCB. As more trace and copper area is placed around the device, θ
JA
decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the dual
or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the
proper package.
TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA
FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT
HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS232C - JUNE 1999 - REVISED AUGUST 2003
21
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Figure 49
100
80
40
0
0 0.25 0.5 0.75
- Maximum RMS Output Current - mA
140
180
1 1.25
160
120
60
20
| V
O
| - RMS Output Voltage - V
I
O
||
Maximum Output
Current Limit Line
TLV2470, TLV2471
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1.5
Safe Operating Area
V
DD
= ± 3 V
T
J
= 150°C
T
A
= 125°C
A
B
C
Packages With
θ
JA
110°C/W
at T
A
= 125°C
or
θ
JA
355°C/W
at T
A
= 70°C
Figure 50
100
80
40
0
0 0.5 1 1.5
- Maximum RMS Output Current - mA
140
180
2 2.5
160
120
60
20
| V
O
| - RMS Output Voltage - V
I
O
||
Maximum Output
Current Limit Line
TLV2470, TLV2471
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating Area
V
DD
= ± 5 V
T
J
= 150°C
T
A
= 125°C
Packages With
θ
JA
210°C/W
at T
A
= 70°C
A
B
C
G
Figure 51
100
80
40
0
0 0.25 0.5 0.75
- Maximum RMS Output Current - mA
140
180
1 1.25
160
120
60
20
| V
O
| - RMS Output Voltage - V
I
O
||
Maximum Output
Current Limit Line
TLV2472, TLV2473
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1.5
C
Safe Operating Area
V
DD
= ± 3 V
T
J
= 150°C
T
A
= 125°C
Packages With
θ
JA
55°C/W
at T
A
= 125°C
or
θ
JA
178°C/W
at T
A
= 70°C
D
G
H
Figure 52
100
80
40
0
0 0.5 1 1.5
- Maximum RMS Output Current - mA
140
180
2 2.5
160
120
60
20
| V
O
| - RMS Output Voltage - V
I
O
||
Maximum Output
Current Limit Line
TLV2472, TLV2473
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating Area
V
DD
= ± 5 V
T
J
= 150°C
T
A
= 125°C
Packages With
θ
JA
105°C/W
at T
A
= 70°C
H
D
C
G
F
A - SOT23(5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP (8); H - PDIP (14); I - PDIP (16);
J - TSSOP PP (14/16)
PREVIOUS12345678910111213NEXT