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SNJ54HCT373J

Part # SNJ54HCT373J
Description Latch Transparent 3-ST 8-CH D-Type 20-Pin CDIP Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 21 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
Eight High-Current Latches in a Single
Package
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HCT373 devices are
transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low,
the Q outputs are latched at the levels that were
set up at the D inputs.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40 C to 85 C
PDIP – N Tube of 20 SN74HCT373N SN74HCT373N
–40 C to 85 C
SOIC – DW
Tube of 25 SN74HCT373DW
HCT373
–40 C to 85 C
SOIC – DW
Reel of 2000 SN74HCT373DWR
HCT373
–40
°
C to 85
°
C
SOP – NS Reel of 2000 SN74HCT373NSR HCT373
–40°C to 85°C
SSOP – DB Reel of 2000 SN74HCT373DBR HT373
TSSOP – PW
Tube of 70 SN74HCT373PW
HT373
TSSOP – PW
Reel of 2000 SN74HCT373PWR
HT373
Reel of 250 SN74HCT373PWT
–55 C to 125 C
CDIP – J Tube of 20 SNJ54HCT373J SNJ54HCT373J
–55
°
C to 125
°
C
CFP – W Tube of 85 SNJ54HCT373W SNJ54HCT373W
LCCC – FK Tube of 55 SNJ54HCT373FK SNJ54HCT373FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D
V
8Q
4Q
GND
LE
SN54HCT373 . . .FK PACKAGE
(TOP VIEW)
CC
SN54HCT373 . . .J OR W PACKAGE
SN74HCT373 . . .DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
OUTPUT
Q
L H H H
L HL L
L LX Q
0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
LE
1D
C1
1D
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT373 SN74HCT373
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage V
CC
= 4.5 V to 5.5 V 2 2 V
V
IL
Low-level input voltage V
CC
= 4.5 V to 5.5 V 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
∆t/∆v Input transition rise/fall time 500 500 ns
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
T
A
= 25°C SN54HCT373 SN74HCT373
UNIT
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
V
OH
I
OH
= –20 µA
4.5 V
4.4 4.499 4.4 4.4
V
V
OH
I
OH
= –6 mA
4.5 V
3.98 4.3 3.7 3.84
V
V
OL
I
OL
= 20 µA
4.5 V
0.001 0.1 0.1 0.1
V
V
OL
I
OL
= 6 mA
4.5 V
0.17 0.26 0.4 0.33
V
I
I
V
I
= V
CC
or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
V
O
= V
CC
or 0 5.5 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
V
I
= V
CC
or 0, I
O
= 0 5.5 V 8 160 80 µA
∆I
CC
†
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
CC
5.5 V 1.4 2.4 3 2.9 mA
C
i
4.5 V
to 5.5 V
3 10 10 10 pF
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
CC
T
A
= 25°C SN54HCT373 SN74HCT373
UNIT
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration, LE high
4.5 V 20 30 25
ns
t
w
Pulse duration, LE high
5.5 V 17 27 23
ns
t
su
Setup time, data before LE↓
4.5 V 10 15 13
ns
t
su
Setup time, data before LE↓
5.5 V 9 14 12
ns
t
h
Hold time, data after LE↓
4.5 V 10 10 10
ns
t
h
Hold time, data after LE↓
5.5 V 10 10 10
ns
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