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SNJ54HC377J

Part # SNJ54HC377J
Description Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin C
Category IC
Availability In Stock
Qty 13
Qty Price
1 - 2 $14.06449
3 - 5 $11.18767
6 - 8 $10.54837
9 - 10 $9.80253
11 + $8.73703
Manufacturer Available Qty
Texas Instruments
Date Code: 9151
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
  
  
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I
CC
D Typical t
pd
= 12 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Eight Flip-Flops With Single-Rail Outputs
D Clock Enable Latched to Avoid False
Clocking
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description/ordering information
These devices are positive-edge-triggered octal
D-type flip-flops with an enable input. The ’HC377
devices are similar to the ’HC273 devices, but
feature a latched clock-enable (CLKEN
) input
instead of a common clear.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse, if CLKEN
is low. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When CLK is at either the
high or low level, the D input has no effect at the
output. These devices are designed to prevent
false clocking by transitions at CLKEN
.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N Tube SN74HC377N SN74HC377N
40°Cto85°C
SOIC DW
Tube SN74HC377DW
HC377
–40°C to 85°C SOIC – DW
Tape and reel SN74HC377DWR
HC377
SOP – NS Tape and reel SN74HC377NSR HC377
CDIP – J Tube SNJ54HC377J SNJ54HC377J
–55°C to 125°C
CFP – W Tube SNJ54HC377W SNJ54HC377W
55 C
to
125 C
LCCC – FK Tube SNJ54HC377FK SNJ54HC377FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
CLKEN
5Q
5D
V
8Q
4Q
GND
CLK
SN54HC377 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC377 ...J OR W PACKAGE
SN74HC377 ...DW, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKEN
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
        
         
       
   
        
       
        
 
  
  
SCLS307B JANUARY 1996 REVISED JANUARY 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLKEN CLK D
OUTPUT
Q
H X X Q
0
L HH
L LL
X L X Q
0
logic diagram (positive logic)
CLKEN
1
11
3
2
CLK
1D
1Q
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
 
  
  
SCLS307B JANUARY 1996 REVISED JANUARY 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC377 SN74HC377
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
V
CC
= 2 V 1.5 1.5
V
IH
High-level input voltage
V
CC
= 4.5 V
3.15 3.15
V
V
IH
High level
in ut
voltage
V
CC
= 6 V 4.2 4.2
V
V
CC
= 2 V 0.5 0.5
V
IL
Low-level input voltage
V
CC
= 4.5 V
1.35 1.35
V
V
IL
Low level
in ut
voltage
V
CC
= 6 V 1.8 1.8
V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
V
CC
= 2 V 1000 1000
t/v Input transition rise/fall time
V
CC
= 4.5 V
500 500
ns
t/v
In ut
transition
rise/fall
time
V
CC
= 6 V 400 400
ns
T
A
Operating free-air temperature 55 125 40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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