Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

SNJ54HC165FK

Part # SNJ54HC165FK
Description Shift Register Single 8-Bit Serial/Parallel to Serial 20-P
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $19.36544
Manufacturer Available Qty
Texas Instruments
Date Code: 9922
  • Shipping Freelance Stock: 2
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
   
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I
CC
D Typical t
pd
= 13 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Complementary Outputs
D Direct Overriding Load (Data) Inputs
D Gated Clock Inputs
D Parallel-to-Serial Data Conversion
SN54HC165 ...J OR W PACKAGE
SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54HC165 . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
SER
CLK INH
H
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Q
H
Q
NC − No internal connection
description/ordering information
The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q
H
)
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD
) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function
and a complementary serial (Q
H
) output.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC165N SN74HC165N
Tube of 40 SN74HC165D
SOIC − D
Reel of 2500 SN74HC165DR
HC165
SOIC − D
Reel of 250 SN74HC165DT
HC165
−40°C to 85°C
SOP − NS Reel of 2000 SN74HC165NSR HC165
−40 C to 85 C
SSOP − DB Reel of 2000 SN74HC165DBR HC165
Tube of 90 SN74HC165PW
TSSOP − PW
Reel of 2000 SN74HC165PWR
HC165
TSSOP − PW
Reel of 250 SN74HC165PWT
HC165
CDIP − J Tube of 25 SNJ54HC165J SNJ54HC165J
−55°C to 125°C
CFP − W Tube of 150 SNJ54HC165W SNJ54HC165W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC165FK SNJ54HC165FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
  !" # $%&" !#  '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+
 '*%$"# $')!" " 122 !)) '!!&"&# !& "&#"&*
%)&## ",&.#& "&*+  !)) ",& '*%$"# '*%$"
'$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+
 
   
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD
is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK CLK INH
FUNCTION
L X X Parallel load
H H X No change
H X H No change
H L Shift
H L Shift
Shift = content of each internal register shifts
toward serial output Q
H
. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
Q
H
Q
H
11 12 13 14 3 4 5 6
ABCDEFGH
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
 
   
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
typical shift, load, and inhibit sequence
Load
E
Q
H
H
G
C
F
Data
Inputs
D
SH/LD
SER
CLK INH
CLK
B
A
Q
H
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
Inhibit Serial Shift
1234567NEXT