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SNJ54BCT8373AFK

Part # SNJ54BCT8373AFK
Description Latch Transparent 3-ST 8-CH D-Type 28-Pin CLLCC Tube
Category IC
Availability Out of Stock
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1 + $9.00000



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F – JUNE 1990 – REVISED JULY 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Octal Test-Integrated Circuits
Functionally Equivalent to ’F373 and
’BCT373 in the Normal-Function Mode
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Test Operation Synchronous to Test
Access Port (TAP)
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V) on TMS Pin
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)
description
The ’BCT8373A scan test devices with octal
D-type latches are members of the Texas
Instruments SCOPE testability integrated-
circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate
testing of complex circuit board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the ’F373 and ’BCT373 octal D-type latches.
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device
terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE octal latches.
In the test mode, the normal operation of the SCOPE octal latches is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary
scan test operations, as described in IEEE Standard 1149.1-1990.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SCOPE is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LE
1Q
2Q
3Q
4Q
GND
5Q
6Q
7Q
8Q
TDO
TMS
OE
1D
2D
3D
4D
5D
V
CC
6D
7D
8D
TDI
TCK
SN54BCT8373A . . . JT PACKAGE
SN74BCT8373A ... DW OR NT PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
8D
TDI
TCK
NC
TMS
TDO
8Q
2D
1D
OE
NC
LE
1Q
2Q
426
14 15 16 17
18
3Q
4Q
GND
NC
5Q
6Q
7Q
3D
4D
5D
NC
V
6D
7D
SN54BCT8373A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
CC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F – JUNE 1990 – REVISED JULY 1996
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test
data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform
other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8373A is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74BCT8373A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(normal mode, each latch)
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
L LX Q
0
H X X Z
logic symbol
SCAN
’BCT8373A
1D
23
1D 1Q
2
TDI
14
TDI
TCK-IN
EN
24
22
2D
2Q
3
TMS
12
TMS
13
TCK
C1
1
LE
TCK-OUT
21
3D 3Q
4
20
4D 4Q
5
19
5D 5Q
7
17
6D 6Q
8
16
7D 7Q
9
15
8D 8Q
10
OE
Φ
TDO
11
TDO
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F – JUNE 1990 – REVISED JULY 1996
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
Boundary-Control
Register
Bypass Register
Boundary-Scan Register
Instruction Register
TDI
TMS
TCK
TDO
TAP
Controller
V
CC
V
CC
OE
V
CC
V
CC
V
CC
LE
1D
V
CC
V
CC
One of Eight Channels
1Q
C1
1D
24
1
23
14
12
13
2
11
Pin numbers shown are for the DW, JT, and NT packages.
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